World's Best Scientists 2026 revealed!

D-Index & Metrics

Electronics and Electrical Engineering

D-Index
43
Citations
11829
World Ranking
3814
National Ranking
1377

Research.com Recognitions

  • 2007 - IEEE Fellow For contributions to common metal oxide semiconductor technology for high-volume manufacturing

Overview

Scott E. Thompson is affiliated with the University of Florida in the United States. Their research spans primarily the field of engineering, with a focus on electrical and electronic engineering, biophysics, artificial intelligence, and computer vision and pattern recognition.

The scientist's recent publications include:

  • Negative Impact of Compressive Biaxial Stress on High Precision Bipolar Devices, 2021, IEEE Transactions on Components Packaging and Manufacturing Technology
  • "Émile Zola and the Naturalistic School, or Realism in French Literature" by Mary Elizabeth Braddon, edited with an Introduction and Textual Notes., 2020, Victorian Popular Fictions Journal
  • WITHDRAWN: Novel machine learning models for flow imaging microscopy sub-visible particle classification in protein formulations, 2023, International Journal of Pharmaceutics
  • Case Study: AI-Driven Early Detection of Cancer Using Deep Learning Models, 2024, International Journal of Emerging Research in Engineering and Technology

Frequent co-authors in their work include:

  • Thomas Weingartner
  • Chiao-Han Kuo
  • Andrew Thomas
  • Mark E. Law
  • Mary Elizabeth

Scott E. Thompson frequently publishes in venues such as:

  • IEEE Transactions on Components Packaging and Manufacturing Technology
  • Victorian Popular Fictions Journal
  • International Journal of Pharmaceutics
  • International Journal of Emerging Research in Engineering and Technology

The main research topics addressed by Thompson include:

  • Electronic Packaging and Soldering Technologies
  • Electrostatic Discharge in Electronics
  • Advanced MEMS and NEMS Technologies
  • Cell Image Analysis Techniques
  • Machine Learning and Data Classification
  • Digital Imaging for Blood Diseases

Among the awards received, Scott E. Thompson was recognized as an IEEE Fellow in 2007 for contributions to common metal oxide semiconductor technology for high-volume manufacturing.

Best Publications

  • A 90nm high volume manufacturing logic technology featuring novel 45nm gate length strained silicon CMOS transistors

    T. Ghani;M. Armstrong;C. Auth;M. Bost

  • Moore's law: the future of Si microelectronics

    Scott E. Thompson;Srivatsan Parthasarathy

  • A 90-nm logic technology featuring strained-silicon

    S.E. Thompson;M. Armstrong;C. Auth;M. Alavi

  • Uniaxial-process-induced strained-Si: extending the CMOS roadmap

    S.E. Thompson;Guangyu Sun;Youn Sung Choi;T. Nishida

  • A logic nanotechnology featuring strained-silicon

    S.E. Thompson;M. Armstrong;C. Auth;S. Cea

  • Physics of strain effects in semiconductors and metal-oxide-semiconductor field-effect transistors

    Y. Sun;S. E. Thompson;T. Nishida

  • MOS Scaling: Transistor Challenges for the 21st Century

    Scott Thompson

  • Strain: A Solution for Higher Carrier Mobility in Nanoscale MOSFETs

    Min Chu;Yongke Sun;Umamaheswari Aghoram;Scott E. Thompson

  • A 90 nm logic technology featuring 50 nm strained silicon channel transistors, 7 layers of Cu interconnects, low k ILD, and 1 /spl mu/m/sup 2/ SRAM cell

    S. Thompson;N. Anand;M. Armstrong;C. Auth

  • Strain effect in semiconductors : theory and device applications

    Yongke Sun;Scott E. Thompson;Toshikazu Nishida

  • Key differences for process-induced uniaxial vs. substrate-induced biaxial stressed Si and Ge channel MOSFETs

    S. Thompson;G. Sun;K. Wu;J. Lim

  • In search of "Forever," continued transistor scaling one new material at a time

    S.E. Thompson;R.S. Chau;T. Ghani;K. Mistry

  • Scaling challenges and device design requirements for high performance sub-50 nm gate length planar CMOS transistors

    T. Ghani;K. Mistry;P. Packan;S. Thompson

  • Comparison of threshold-voltage shifts for uniaxial and biaxial tensile-stressed n-MOSFETs

    Ji-Song Lim;S.E. Thompson;J.G. Fossum

  • Electronic devices and systems, and methods for making and using the same

    Scott E. Thompson;Damodar R. Thummalapally

  • Delaying forever: Uniaxial strained silicon transistors in a 90nm CMOS technology

    K. Mistry;M. Armstrong;C. Auth;S. Cea

  • Strain Effect in Semiconductors

    Yongke Sun;Scott E. Thompson;Toshikazu Nishida

  • CMOS fabrication process utilizing special transistor orientation

    Mark Armstrong;Gerhard Schrom;Sunit Tyagi;Paul A. Packan

  • A 130 nm generation logic technology featuring 70 nm transistors, dual Vt transistors and 6 layers of Cu interconnects

    S. Tyagi;M. Alavi;R. Bigwood;T. Bramblett

  • Hole mobility in silicon inversion layers: Stress and surface orientation

    Guangyu Sun;Yongke Sun;Toshikazu Nishida;Scott E. Thompson

  • Transistor with threshold voltage set notch and method of fabrication thereof

    Reza Arghavani;Pushkar Ranade;Lucian Shifren;Scott E. Thompson

Frequent Co-Authors

Toshikazu Nishida
Toshikazu Nishida University of Florida
Mark T. Bohr
Mark T. Bohr Intel (United States)
Tahir Ghani
Tahir Ghani Intel (United States)
Prashant Majhi
Prashant Majhi Intel (United States)
Muhammad Mustafa Hussain
Muhammad Mustafa Hussain Purdue University West Lafayette
Paul Kirsch
Paul Kirsch Samsung Austin Semiconductor
Ronald D. Schrimpf
Ronald D. Schrimpf Vanderbilt University
Byoung Hun Lee
Byoung Hun Lee Pohang University of Science and Technology
Daniel M. Fleetwood
Daniel M. Fleetwood Vanderbilt University
Rino Choi
Rino Choi Inha University

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