World's Best Scientists 2026 revealed!

D-Index & Metrics

Electronics and Electrical Engineering

D-Index
57
Citations
13165
World Ranking
1959
National Ranking
771

Research.com Recognitions

  • 2012 - IEEE Jun-ichi Nishizawa Medal “For sustained leadership in developing innovative transistor technologies for advanced logic products.”
  • 2005 - Member of the National Academy of Engineering For leadership in defining, developing, and implementing a manufacturable CMOS/BiCMOS technology for microprocessor and logic products.

Overview

What is he best known for?

The fields of study he is best known for:

  • Integrated circuit
  • Electrical engineering
  • Transistor

Mark T. Bohr mainly investigates Transistor, Electrical engineering, Optoelectronics, MOSFET and Integrated circuit. The study incorporates disciplines such as CMOS and Embedded system in addition to Transistor. His Electrical engineering study integrates concerns from other disciplines, such as Capacitance, Electronic engineering and Conductor.

Mark T. Bohr combines subjects such as Layer, Substrate and Field-effect transistor with his study of Optoelectronics. His MOSFET research is multidisciplinary, incorporating perspectives in Switching time, Logic gate and Voltage control. Mark T. Bohr interconnects Structural engineering, Electrically conductive, Interposer and Electrical element in the investigation of issues within Integrated circuit.

His most cited work include:

  • A logic nanotechnology featuring strained-silicon (493 citations)
  • Interconnect scaling-the real limiter to high performance ULSI (468 citations)
  • A 90 nm logic technology featuring 50 nm strained silicon channel transistors, 7 layers of Cu interconnects, low k ILD, and 1 /spl mu/m/sup 2/ SRAM cell (277 citations)

What are the main themes of his work throughout his whole career to date?

His main research concerns Optoelectronics, Electrical engineering, Transistor, Electronic engineering and Layer. The study incorporates disciplines such as Substrate and Interconnection in addition to Optoelectronics. His Electrical engineering research includes themes of Die and Reliability.

His Transistor study combines topics in areas such as CMOS and Leakage. The concepts of his Electronic engineering study are interwoven with issues in Capacitance, Wafer, Oxide and Silicon nitride. In general Layer, his work in Substrate and Passivation is often linked to Fabrication linking many areas of study.

He most often published in these fields:

  • Optoelectronics (53.24%)
  • Electrical engineering (33.81%)
  • Transistor (32.37%)

What were the highlights of his more recent work (between 2011-2020)?

  • Optoelectronics (53.24%)
  • Integrated circuit (26.62%)
  • Electrical engineering (33.81%)

In recent papers he was focusing on the following fields of study:

Optoelectronics, Integrated circuit, Electrical engineering, Interconnection and Transistor are his primary areas of study. His Optoelectronics research incorporates elements of Layer and Substrate. The various areas that he examines in his Integrated circuit study include Die and Cache.

His NMOS logic and PMOS logic study in the realm of Electrical engineering connects with subjects such as Strain and Stack. His Interconnection study which covers Semiconductor that intersects with Base, Die and Fin. His research integrates issues of Silicon, CMOS, Logic gate, Static random-access memory and Moore's law in his study of Transistor.

Between 2011 and 2020, his most popular works were:

  • A 4.6GHz 162Mb SRAM design in 22nm tri-gate CMOS technology with integrated active V MIN -enhancing assist circuitry (99 citations)
  • Gate contact structure over active gate and method to fabricate same (82 citations)
  • CMOS Scaling Trends and Beyond (76 citations)

In his most recent research, the most cited papers focused on:

  • Electrical engineering
  • Integrated circuit
  • Semiconductor

His primary areas of investigation include Optoelectronics, Transistor, Electrical engineering, Die and Electronic engineering. Mark T. Bohr studies Semiconductor, a branch of Optoelectronics. His Transistor research incorporates themes from CMOS, Silicon and Integrated circuit.

His research on Electrical engineering frequently connects to adjacent areas such as Substrate. His research in Die tackles topics such as Routing which are related to areas like Mechanical engineering, Layer, Redistribution layer, Molding and Substrate. His Electronic engineering study combines topics from a wide range of disciplines, such as Fin and Self-aligned gate.

Best Publications

  • A 90nm high volume manufacturing logic technology featuring novel 45nm gate length strained silicon CMOS transistors

    T. Ghani;M. Armstrong;C. Auth;M. Bost

  • A 90-nm logic technology featuring strained-silicon

    S.E. Thompson;M. Armstrong;C. Auth;M. Alavi

  • Interconnect scaling-the real limiter to high performance ULSI

    M.T. Bohr

  • A logic nanotechnology featuring strained-silicon

    S.E. Thompson;M. Armstrong;C. Auth;S. Cea

  • A 3-GHz 70-mb SRAM in 65-nm CMOS technology with integrated column-based dynamic power supply

    Kevin Zhang;U. Bhattacharya;Zhanping Chen;F. Hamzaoglu

  • The High-k Solution

    M.T. Bohr;R.S. Chau;T. Ghani;K. Mistry

  • A 90 nm logic technology featuring 50 nm strained silicon channel transistors, 7 layers of Cu interconnects, low k ILD, and 1 /spl mu/m/sup 2/ SRAM cell

    S. Thompson;N. Anand;M. Armstrong;C. Auth

  • A 65nm logic technology featuring 35nm gate lengths, enhanced channel strain, 8 Cu interconnect layers, low-k ILD and 0.57 /spl mu/m/sup 2/ SRAM cell

    P. Bai;C. Auth;S. Balakrishnan;M. Bost

  • A 30 Year Retrospective on Dennard's MOSFET Scaling Paper

    Mark Bohr

  • CMOS Scaling Trends and Beyond

    Mark T. Bohr;Ian A. Young

  • SRAM design on 65-nm CMOS technology with dynamic sleep transistor for leakage reduction

    K. Zhang;U. Bhattacharya;Zhanping Chen;F. Hamzaoglu

  • Method of making an interposer

    Mark T. Bohr

  • In search of "Forever," continued transistor scaling one new material at a time

    S.E. Thompson;R.S. Chau;T. Ghani;K. Mistry

  • Scaling challenges and device design requirements for high performance sub-50 nm gate length planar CMOS transistors

    T. Ghani;K. Mistry;P. Packan;S. Thompson

  • Diffusion of copper through dielectric films under bias temperature stress

    Gopal Raghavan;Chien Chiang;Paul B. Anders;Sing-Mo Tzeng

  • A 4.6GHz 162Mb SRAM design in 22nm tri-gate CMOS technology with integrated active V MIN -enhancing assist circuitry

    Eric Karl;Yih Wang;Yong-Gee Ng;Zheng Guo

  • The new era of scaling in an SoC world

    Mark Bohr

  • Delaying forever: Uniaxial strained silicon transistors in a 90nm CMOS technology

    K. Mistry;M. Armstrong;C. Auth;S. Cea

  • The evolution of scaling from the homogeneous era to the heterogeneous era

    Mark Bohr

  • A 130 nm generation logic technology featuring 70 nm transistors, dual Vt transistors and 6 layers of Cu interconnects

    S. Tyagi;M. Alavi;R. Bigwood;T. Bramblett

  • A 3-GHz 70MB SRAM in 65nm CMOS technology with integrated column-based dynamic power supply

    Unknown

Frequent Co-Authors

Tahir Ghani
Tahir Ghani Intel (United States)
Kevin Zhang
Kevin Zhang Taiwan Semiconductor Manufacturing Company (Taiwan)
Fatih Hamzaoglu
Fatih Hamzaoglu Intel (United States)
Scott E. Thompson
Scott E. Thompson University of Florida
Anand S. Murthy
Anand S. Murthy Intel (United States)
Robert S. Chau
Robert S. Chau Intel (United States)
Mark L. Doczy
Mark L. Doczy Intel (United States)
Justin K. Brask
Justin K. Brask Intel (United States)
Suman Datta
Suman Datta Georgia Institute of Technology

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