World's Best Scientists 2026 revealed!

D-Index & Metrics

Electronics and Electrical Engineering

D-Index
52
Citations
9069
World Ranking
2555
National Ranking
973

Materials Science

D-Index
54
Citations
9403
World Ranking
8979
National Ranking
2194

Overview

What is he best known for?

The fields of study he is best known for:

  • Semiconductor
  • Transistor
  • Silicon

Mark L. Doczy focuses on Optoelectronics, Gate oxide, Layer, Gate dielectric and Semiconductor device. His Optoelectronics study integrates concerns from other disciplines, such as Metal gate, Transistor and Substrate. His biological study spans a wide range of topics, including PMOS logic, Dielectric layer, Metal and Polysilicon depletion effect.

The Transistor study combines topics in areas such as Substrate, Nanotechnology, Silicon and Engineering physics. In Gate dielectric, he works on issues like High-κ dielectric, which are connected to Time-dependent gate oxide breakdown, Silicon dioxide, Atomic layer deposition and Zirconium dioxide. His study focuses on the intersection of Semiconductor device and fields such as Trench with connections in the field of Hard mask.

His most cited work include:

  • Nonplanar transistors with metal gate electrodes (390 citations)
  • Method for making a semiconductor device having a high-k gate dielectric (257 citations)
  • Block Contact Architectures for Nanoscale Channel Transistors (217 citations)

What are the main themes of his work throughout his whole career to date?

Mark L. Doczy spends much of his time researching Optoelectronics, Layer, Gate oxide, Gate dielectric and Metal gate. His Optoelectronics research incorporates elements of Transistor, Semiconductor device and Metal. His work carried out in the field of Transistor brings together such families of science as CMOS, Nanotechnology and Work function.

His work on Substrate and Tunnel magnetoresistance as part of general Layer research is frequently linked to Stack and Perpendicular, bridging the gap between disciplines. Mark L. Doczy combines subjects such as High-κ dielectric and Semiconductor with his study of Gate dielectric. His Metal gate research integrates issues from PMOS logic, NMOS logic and Polysilicon depletion effect.

He most often published in these fields:

  • Optoelectronics (72.45%)
  • Layer (53.57%)
  • Gate oxide (28.06%)

What were the highlights of his more recent work (between 2015-2019)?

  • Layer (53.57%)
  • Optoelectronics (72.45%)
  • Tunnel magnetoresistance (16.84%)

In recent papers he was focusing on the following fields of study:

Mark L. Doczy mostly deals with Layer, Optoelectronics, Tunnel magnetoresistance, Stack and Perpendicular. Substrate is the focus of his Layer research. His Optoelectronics study deals with Electrical conductor intersecting with Nano-.

His Tunnel magnetoresistance research includes elements of Magnetic layer, Tunnel barrier and Cobalt. His Metal study integrates concerns from other disciplines, such as Thermal conduction and Low resistance. His work is dedicated to discovering how Composite material, Dielectric are connected with Semiconductor device, Protection layer and Pillar and other disciplines.

Between 2015 and 2019, his most popular works were:

  • Approaches for strain engineering of perpendicular magnetic tunnel junctions (pmtjs) and the resulting structures (8 citations)
  • Ferromagnetic resonance testing of buried magnetic layers of whole wafer (5 citations)
  • SPIN ORBIT TORQUE (SOT) MEMORY DEVICES WITH ENHANCED TUNNEL MAGNETORESISTANCE RATIO AND THEIR METHODS OF FABRICATION (4 citations)

In his most recent research, the most cited papers focused on:

  • Semiconductor
  • Layer
  • Silicon

His primary areas of investigation include Layer, Tunnel magnetoresistance, Optoelectronics, Perpendicular and Substrate. The Layer study combines topics in areas such as Alloy, Spin-transfer torque, Quantum tunnelling and Dielectric. His research integrates issues of Semiconductor device, Pillar and Protection layer in his study of Dielectric.

As a part of the same scientific study, Mark L. Doczy usually deals with the Tunnel magnetoresistance, concentrating on Magnetic layer and frequently concerns with Thermal stability and Spin orbit torque. His work on Dielectric layer as part of general Optoelectronics study is frequently connected to Stack, therefore bridging the gap between diverse disciplines of science and establishing a new relationship between them. His Dielectric layer research is multidisciplinary, incorporating perspectives in Electrical conductor and Diffusion barrier.

Best Publications

  • High-/spl kappa//metal-gate stack and its MOSFET characteristics

    R. Chau;S. Datta;M. Doczy;B. Doyle

  • Nonplanar transistors with metal gate electrodes

    Justin K. Brask;Brian S. Doyle;Mark L. Doczy;Robert S. Chau

  • Method of forming a nonplanar transistor with sidewall spacers

    Justin K. Brask;Brian S. Doyle;Jack Kavalieros;Mark Doczy

  • Tri-Gate fully-depleted CMOS transistors: fabrication, design and layout

    B. Doyle;B. Boyanov;S. Datta;M. Doczy

  • Block Contact Architectures for Nanoscale Channel Transistors

    Marko Radosavljevic;Amlan Majumdar;Brian S. Doyle;Jack Kavalieros

  • Tri-Gate Transistor Architecture with High-k Gate Dielectrics, Metal Gates and Strain Engineering

    J. Kavalieros;B. Doyle;S. Datta;G. Dewey

  • Method for making a semiconductor device having a high-k gate dielectric layer and a metal gate electrode

    Justin K. Brask;Jack Kavalieros;Mark L. Doczy;Uday Shah

  • Method for making a semiconductor device having a high-k gate dielectric

    Mark L. Doczy;Gilbert Dewey;Suman Datta;Sangwoo Pae

  • Atomic layer deposition of high dielectric constant gate dielectrics

    Matthew Metz;Clifford Boyd;Markus Kuhn;Suman Datta

  • Complementary metal oxide semiconductor integrated circuit using raised source drain and replacement metal gate

    Jack Kavalieros;Annalisa Cappellani;Justin K. Brask;Mark L. Doczy

  • Application of high-κ gate dielectrics and metal gate electrodes to enable silicon and non-silicon logic nanotechnology

    Robert Chau;Justin Brask;Suman Datta;Gilbert Dewey

  • Integrated circuit with metal gate electrode and method for manufacturing metal gate electrode

    Mark Doczy;Chris Barns;Jack Kavalieros;Suman Datta

  • Method for making a semiconductor device that includes a metal gate electrode

    Mark L. Doczy;Justin K. Brask;Jack Kavalieros;Uday Shah

  • Replacement gate process for making a semiconductor device that includes a metal gate electrode

    Uday Shah;Chris E. Barns;Mark L. Doczy;Justin K. Brask

  • Process for integrating planar and non-planar cmos transistors on a bulk substrate and article made thereby

    Jack T. Kavalieros;Justin K. Brask;Brian S. Doyle;Uday Shah

  • Metalgate electrode for PMOS transistor

    Robert Chau;Mark Doczy;Brian Doyle;Jack Kavalieros

  • Transition metal alloy, device incorporating the same and method of forming a device including the same

    Baxter Nathan;Chau Robert S;Harkonen Kari;Lang Teemu

  • Semiconductor device with a high-k gate dielectric and a metal gate electrode

    Mark L. Doczy;Jack Kavalieros;Matthew V. Metz;Justin K. Brask

  • CMOS-compatible synthesis of large-area, high-mobility graphene by chemical vapor deposition of acetylene on cobalt thin films

    Michael E. Ramón;Aparna Gupta;Chris Corbet;Domingo A. Ferrer

  • Advanced Depleted-Substrate Transistors: Single-gate, Double-gate and Tri-gate

    Robert Chau;Brian Doyle;Jack Kavalieros;Doug Barlage

  • High- /Metal-Gate Stack and Its MOSFET Characteristics

    Robert Chau;Suman Datta;Mark Doczy;Brian Doyle

Frequent Co-Authors

Robert S. Chau
Robert S. Chau Intel (United States)
Justin K. Brask
Justin K. Brask Intel (United States)
Brian S. Doyle
Brian S. Doyle Intel (United States)
jack t kavalieros
jack t kavalieros Intel (United States)
Suman Datta
Suman Datta Georgia Institute of Technology
Uday Shah
Uday Shah Intel (United States)
matthew v metz
matthew v metz Intel (United States)
Tahir Ghani
Tahir Ghani Intel (United States)
Marko Radosavljevic
Marko Radosavljevic Intel (United States)
Anand S. Murthy
Anand S. Murthy Intel (United States)

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