World's Best Scientists 2026 revealed!

D-Index & Metrics

Electronics and Electrical Engineering

D-Index
78
Citations
17381
World Ranking
593
National Ranking
263

Materials Science

D-Index
79
Citations
17633
World Ranking
2888
National Ranking
812

Overview

What is he best known for?

The fields of study he is best known for:

  • Semiconductor
  • Transistor
  • Optoelectronics

Jack T. Kavalieros spends much of his time researching Optoelectronics, Transistor, Layer, Substrate and Gate oxide. His studies deal with areas such as Metal gate, Electronic engineering and Semiconductor device as well as Optoelectronics. Jack T. Kavalieros interconnects Substrate, Nanotechnology and Fin in the investigation of issues within Transistor.

His Layer research integrates issues from Silicon and Silicon-germanium. His work carried out in the field of Substrate brings together such families of science as Barrier layer, Work function, Dielectric and Germanium. His Gate oxide research incorporates elements of High-κ dielectric and Gate dielectric.

His most cited work include:

  • Tri-gate devices and methods of fabrication (557 citations)
  • Integrated nanoelectronics for the future (294 citations)
  • Non-planar gate all-around device and method of fabrication thereof (284 citations)

What are the main themes of his work throughout his whole career to date?

Jack T. Kavalieros focuses on Optoelectronics, Transistor, Layer, Substrate and Gate dielectric. The concepts of his Optoelectronics study are interwoven with issues in Electronic engineering, Semiconductor device, Electrical engineering and Gate oxide. The various areas that he examines in his Transistor study include Nanowire, CMOS, Silicon and Substrate.

His work in the fields of Layer, such as Trench, Barrier layer and Epitaxy, intersects with other areas such as Stack. Jack T. Kavalieros combines subjects such as Dopant and Germanium with his study of Substrate. His study in Gate dielectric is interdisciplinary in nature, drawing from both High-κ dielectric, Dielectric and Thin-film transistor.

He most often published in these fields:

  • Optoelectronics (83.67%)
  • Transistor (48.98%)
  • Layer (40.52%)

What were the highlights of his more recent work (between 2017-2020)?

  • Optoelectronics (83.67%)
  • Transistor (48.98%)
  • Layer (40.52%)

In recent papers he was focusing on the following fields of study:

The scientist’s investigation covers issues in Optoelectronics, Transistor, Layer, Gate dielectric and Substrate. His Optoelectronics research is multidisciplinary, relying on both Semiconductor device and Thin-film transistor. His work on Memory cell as part of general Transistor research is frequently linked to Fin, thereby connecting diverse disciplines of science.

His Epitaxy, Trench and Active layer study in the realm of Layer connects with subjects such as Stack. The study incorporates disciplines such as Buffer and Silicon in addition to Substrate. His research integrates issues of Gate oxide and Strain engineering in his study of Ferroelectricity.

Between 2017 and 2020, his most popular works were:

  • TRANSISTOR SOURCE/DRAIN AMORPHOUS INTERLAYER ARRANGEMENTS (31 citations)
  • CHARGE TRAP LAYER IN BACK-GATED THIN-FILM TRANSISTORS (2 citations)
  • APPLICATIONS OF BACK-END-OF-LINE (BEOL) CAPACITORS IN COMPUTE-IN-MEMORY (CIM) CIRCUITS (2 citations)

In his most recent research, the most cited papers focused on:

  • Semiconductor
  • Transistor
  • Electrical engineering

Jack T. Kavalieros mainly investigates Optoelectronics, Transistor, Layer, Semiconductor and Capacitor. His research is interdisciplinary, bridging the disciplines of Substrate and Optoelectronics. His work on Gate dielectric as part of general Transistor study is frequently connected to Fin, therefore bridging the gap between diverse disciplines of science and establishing a new relationship between them.

His Gate dielectric study deals with Dielectric intersecting with Contact electrode and Conformal map. His Semiconductor research incorporates themes from Oxide semiconductor, Amorphous oxide and Memory cell. His study on Capacitor also encompasses disciplines like

  • Composite material which connect with Semimetal, Thin film, Tetragonal crystal system and Strain engineering,
  • Trench that intertwine with fields like Buffer, Field-effect transistor and Semiconductor device,
  • Ferroelectricity, which have a strong connection to Dram and Memory architecture.

Best Publications

  • TRI-GATE DEVICE AND MANUFACTURING METHOD

    Chau Robert;Doyle Brian;Kavalieros Jack;Barlage Douglas

  • High performance fully-depleted tri-gate CMOS transistors

    B.S. Doyle;S. Datta;M. Doczy;S. Hareland

  • Integrated nanoelectronics for the future

    Robert Chau;Brian Doyle;Suman Datta;Jack Kavalieros

  • Fabrication, characterization, and physics of III–V heterojunction tunneling Field Effect Transistors (H-TFET) for steep sub-threshold swing

    G. Dewey;B. Chu-Kung;J. Boardman;J. M. Fastenau

  • Semiconductor device and integrated circuit structure

    Rachmady Willy;Pillarisetty Ravi;Le Van H;Kavalieros Jack T

  • Method of forming a nonplanar transistor with sidewall spacers

    Justin K. Brask;Brian S. Doyle;Jack Kavalieros;Mark Doczy

  • Tri-Gate fully-depleted CMOS transistors: fabrication, design and layout

    B. Doyle;B. Boyanov;S. Datta;M. Doczy

  • Block Contact Architectures for Nanoscale Channel Transistors

    Marko Radosavljevic;Amlan Majumdar;Brian S. Doyle;Jack Kavalieros

  • Method for making a semiconductor device having a high-k gate dielectric layer and a metal gate electrode

    Justin K. Brask;Jack Kavalieros;Mark L. Doczy;Uday Shah

  • A 50 nm depleted-substrate CMOS transistor (DST)

    R. Chau;J. Kavalieros;B. Doyle;A. Murthy

  • Method for making a semiconductor device having a high-k gate dielectric

    Mark L. Doczy;Gilbert Dewey;Suman Datta;Sangwoo Pae

  • Forming a type i heterostructure in a group iv semiconductor

    Chi On Chui;Prashant Majhi;Wilman Tsai;Jack T. Kavalieros

  • CMOS devices with a single work function gate electrode and method of fabrication

    Brian S. Doyle;Been-Yih Jin;Jack T. Kavalieros;Suman Datta

  • Atomic layer deposition of high dielectric constant gate dielectrics

    Matthew Metz;Clifford Boyd;Markus Kuhn;Suman Datta

  • Direct-current measurements of oxide and interface traps on oxidized silicon

    A. Neugroschel;Chih-Tang Sah;K.M. Han;M.S. Carroll

  • Advanced high-K gate dielectric for high-performance short-channel In 0.7 Ga 0.3 As quantum well field effect transistors on silicon substrate for low power logic applications

    M. Radosavljevic;B. Chu-Kung;S. Corcoran;G. Dewey

  • SRAM and logic transistors with variable height multi-gate transistor architecture

    Suman Datta;Brian S. Doyle;Jack T. Kavalieros;Yih Wang

  • Complementary metal oxide semiconductor integrated circuit using raised source drain and replacement metal gate

    Jack Kavalieros;Annalisa Cappellani;Justin K. Brask;Mark L. Doczy

  • 6t finfet cmos sram cell with an increased cell ratio

    Suman Datta;Brian Doyle;Robert Chau;Jack Kavalieros

  • Application of high-κ gate dielectrics and metal gate electrodes to enable silicon and non-silicon logic nanotechnology

    Robert Chau;Justin Brask;Suman Datta;Gilbert Dewey

  • Integrated circuit with metal gate electrode and method for manufacturing metal gate electrode

    Mark Doczy;Chris Barns;Jack Kavalieros;Suman Datta

Frequent Co-Authors

Robert S. Chau
Robert S. Chau Intel (United States)
Suman Datta
Suman Datta Georgia Institute of Technology
Marko Radosavljevic
Marko Radosavljevic Intel (United States)
Justin K. Brask
Justin K. Brask Intel (United States)
matthew v metz
matthew v metz Intel (United States)
Brian S. Doyle
Brian S. Doyle Intel (United States)
Mark L. Doczy
Mark L. Doczy Intel (United States)
Tahir Ghani
Tahir Ghani Intel (United States)
Anand S. Murthy
Anand S. Murthy Intel (United States)
Uday Shah
Uday Shah Intel (United States)

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