World's Best Scientists 2026 revealed!

D-Index & Metrics

Electronics and Electrical Engineering

D-Index
48
Citations
8518
World Ranking
3094
National Ranking
1161

Materials Science

D-Index
48
Citations
8555
World Ranking
10835
National Ranking
2560

Overview

What is he best known for?

The fields of study he is best known for:

  • Semiconductor
  • Transistor
  • Integrated circuit

Matthew V. Metz focuses on Optoelectronics, High-κ dielectric, Gate dielectric, Gate oxide and Transistor. His Optoelectronics study combines topics from a wide range of disciplines, such as Field-effect transistor, Metal gate, Substrate and PMOS logic. His studies deal with areas such as Inorganic chemistry, Zirconium and Logic gate as well as High-κ dielectric.

His Gate oxide research incorporates elements of Electronic engineering and Semiconductor device. His study with Transistor involves better knowledge in Electrical engineering. Matthew V. Metz has researched Nanotechnology in several fields, including Electronic circuit, Moore's law and Subthreshold slope.

His most cited work include:

  • Benchmarking nanotechnology for high-performance and low-power logic transistor applications (592 citations)
  • High-/spl kappa//metal-gate stack and its MOSFET characteristics (365 citations)
  • Method for making a semiconductor device having a high-k gate dielectric (257 citations)

What are the main themes of his work throughout his whole career to date?

The scientist’s investigation covers issues in Optoelectronics, Transistor, Layer, Gate dielectric and Substrate. His research integrates issues of Semiconductor device, Electrical engineering and Gate oxide in his study of Optoelectronics. His research in Gate oxide intersects with topics in Electron mobility, Electronic engineering and Silicon, Silicon-germanium.

His studies in Transistor integrate themes in fields like CMOS and Nanotechnology. His study on Trench, Substrate and Barrier layer is often connected to Stack as part of broader study in Layer. His Substrate study which covers Chemical engineering that intersects with Inorganic chemistry.

He most often published in these fields:

  • Optoelectronics (76.69%)
  • Transistor (39.10%)
  • Layer (36.09%)

What were the highlights of his more recent work (between 2019-2021)?

  • Optoelectronics (76.69%)
  • Transistor (39.10%)
  • Gate dielectric (34.59%)

In recent papers he was focusing on the following fields of study:

Matthew V. Metz mainly focuses on Optoelectronics, Transistor, Gate dielectric, Communication channel and Layer. His study in Optoelectronics is interdisciplinary in nature, drawing from both Semiconductor device, Substrate and NMOS logic. His research investigates the connection between Semiconductor device and topics such as Field-effect transistor that intersect with problems in Trench.

His work deals with themes such as Moore's law, CMOS, Metal gate and Inverter, which intersect with NMOS logic. His research related to PMOS logic and Gate oxide might be considered part of Transistor. His Gate oxide research includes elements of Nanowire, Semiconductor and Metal electrodes.

Between 2019 and 2021, his most popular works were:

  • High Speed Memory Operation in Channel-Last, Back-gated Ferroelectric Transistors (1 citations)
  • 3-D Self-aligned Stacked NMOS-on-PMOS Nanoribbon Transistors for Continued Moore’s Law Scaling (1 citations)
  • CMOS Compatible Process Integration of SOT-MRAM with Heavy-Metal Bi-Layer Bottom Electrode and 10ns Field-Free SOT Switching with STT Assist (1 citations)

In his most recent research, the most cited papers focused on:

  • Semiconductor
  • Transistor
  • Integrated circuit

His primary areas of investigation include Optoelectronics, Semiconductor, Communication channel, Transistor and Logic gate. The concepts of his Optoelectronics study are interwoven with issues in Moore's law and Substrate, Gate oxide. His work carried out in the field of Moore's law brings together such families of science as Metal gate, NMOS logic, CMOS, PMOS logic and Inverter.

His Substrate research includes themes of Field-effect transistor, Trench, Semiconductor device and Buffer. His research on Gate oxide often connects related areas such as Ferroelectricity. His studies in Integrated circuit integrate themes in fields like Self-aligned gate and Fin.

Best Publications

  • Benchmarking nanotechnology for high-performance and low-power logic transistor applications

    R. Chau;S. Datta;M. Doczy;B. Doyle

  • High-/spl kappa//metal-gate stack and its MOSFET characteristics

    R. Chau;S. Datta;M. Doczy;B. Doyle

  • Fabrication, characterization, and physics of III–V heterojunction tunneling Field Effect Transistors (H-TFET) for steep sub-threshold swing

    G. Dewey;B. Chu-Kung;J. Boardman;J. M. Fastenau

  • Tri-Gate Transistor Architecture with High-k Gate Dielectrics, Metal Gates and Strain Engineering

    J. Kavalieros;B. Doyle;S. Datta;G. Dewey

  • Method for making a semiconductor device having a high-k gate dielectric layer and a metal gate electrode

    Justin K. Brask;Jack Kavalieros;Mark L. Doczy;Uday Shah

  • Method for making a semiconductor device having a high-k gate dielectric

    Mark L. Doczy;Gilbert Dewey;Suman Datta;Sangwoo Pae

  • Atomic layer deposition of high dielectric constant gate dielectrics

    Matthew Metz;Clifford Boyd;Markus Kuhn;Suman Datta

  • Advanced high-K gate dielectric for high-performance short-channel In 0.7 Ga 0.3 As quantum well field effect transistors on silicon substrate for low power logic applications

    M. Radosavljevic;B. Chu-Kung;S. Corcoran;G. Dewey

  • Complementary metal oxide semiconductor integrated circuit using raised source drain and replacement metal gate

    Jack Kavalieros;Annalisa Cappellani;Justin K. Brask;Mark L. Doczy

  • Application of high-κ gate dielectrics and metal gate electrodes to enable silicon and non-silicon logic nanotechnology

    Robert Chau;Justin Brask;Suman Datta;Gilbert Dewey

  • Replacement gate process for making a semiconductor device that includes a metal gate electrode

    Uday Shah;Chris E. Barns;Mark L. Doczy;Justin K. Brask

  • Process for integrating planar and non-planar cmos transistors on a bulk substrate and article made thereby

    Jack T. Kavalieros;Justin K. Brask;Brian S. Doyle;Uday Shah

  • Electrostatics improvement in 3-D tri-gate over ultra-thin body planar InGaAs quantum well field effect transistors with high-K gate dielectric and scaled gate-to-drain/gate-to-source separation

    M. Radosavljevic;G. Dewey;D. Basu;J. Boardman

  • High mobility strained germanium quantum well field effect transistor as the p-channel device option for low power (Vcc = 0.5 V) III–V CMOS architecture

    R. Pillarisetty;B. Chu-Kung;S. Corcoran;G. Dewey

  • Semiconductor device with a high-k gate dielectric and a metal gate electrode

    Mark L. Doczy;Jack Kavalieros;Matthew V. Metz;Justin K. Brask

  • BTI reliability of 45 nm high-K + metal-gate process technology

    S. Pae;M. Agostinelli;M. Brazier;R. Chau

  • Field effect transistor with narrow bandgap source and drain regions and method of fabrication

    Robert S. Chau;Suman Datta;Jack Kavalieros;Justin K. Brask

  • Non-planar, multi-gate InGaAs quantum well field effect transistors with high-K gate dielectric and ultra-scaled gate-to-drain/gate-to-source separation for low power logic applications

    M. Radosavljevic;G. Dewey;J. M. Fastenau;J. Kavalieros

  • 300mm Heterogeneous 3D Integration of Record Performance Layer Transfer Germanium PMOS with Silicon NMOS for Low Power High Performance Logic Applications

    W. Rachmady;K. Jun;B. Krist;M. Metz

  • High mobility Si/SiGe strained channel MOS transistors with HfO/sub 2//TiN gate stack

    S. Datta;G. Dewey;M. Doczy;B.S. Doyle

Frequent Co-Authors

jack t kavalieros
jack t kavalieros Intel (United States)
Robert S. Chau
Robert S. Chau Intel (United States)
Suman Datta
Suman Datta Georgia Institute of Technology
Mark L. Doczy
Mark L. Doczy Intel (United States)
Justin K. Brask
Justin K. Brask Intel (United States)
Marko Radosavljevic
Marko Radosavljevic Intel (United States)
Uday Shah
Uday Shah Intel (United States)
Tahir Ghani
Tahir Ghani Intel (United States)
Anand S. Murthy
Anand S. Murthy Intel (United States)
Brian S. Doyle
Brian S. Doyle Intel (United States)

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