Tahir Ghani

Research.com Recognitions

• 2015 - Member of the National Academy of Engineering For development of transistor technologies for logic products.
• 2012 - IEEE Jun-ichi Nishizawa Medal “For sustained leadership in developing innovative transistor technologies for advanced logic products.”
• 2009 - IEEE Fellow For contributions to deep submicron metal oxide semiconductor transistor development for microprocessors

Overview

Best Publications

• A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging

  K. Mistry;C. Allen;C. Auth;B. Beattie

  1547
  Citations

• A 90nm high volume manufacturing logic technology featuring novel 45nm gate length strained silicon CMOS transistors

  T. Ghani;M. Armstrong;C. Auth;M. Bost

  1007
  Citations

• A 22nm high performance and low-power CMOS technology featuring fully-depleted tri-gate transistors, self-aligned contacts and high density MIM capacitors

  C. Auth;C. Allen;A. Blattner;D. Bergstrom

  973
  Citations

• A 90-nm logic technology featuring strained-silicon

  S.E. Thompson;M. Armstrong;C. Auth;M. Alavi

  937
  Citations

• A logic nanotechnology featuring strained-silicon

  S.E. Thompson;M. Armstrong;C. Auth;S. Cea

  689
  Citations

• Semiconductor transistor having a stressed channel

  Anand Murthy;Robert S. Chau;Tahir Ghani;Kaizad R. Mistry

  538
  Citations

• A 14nm logic technology featuring 2 nd -generation FinFET, air-gapped interconnects, self-aligned double patterning and a 0.0588 µm 2 SRAM cell size

  S. Natarajan;M. Agostinelli;S. Akbar;M. Bost

  525
  Citations

• The High-k Solution

  M.T. Bohr;R.S. Chau;T. Ghani;K. Mistry

  502
  Citations

• 45nm High-k + metal gate strain-enhanced transistors

  C. Auth;A. Cappellani;J.-S. Chun;A. Dalis

  497
  Citations

• METHOD AND DEVICE FOR IMPROVING SALICIDE RESISTANCE ON POLYCRYSTAL SILICON GATE

  Jan Chia-Hong;Tsai Julie A;Yang Simon;Ghani Tahir

  472
  Citations

• The future transistors

  Unknown

  469
  Citations

• A 90 nm logic technology featuring 50 nm strained silicon channel transistors, 7 layers of Cu interconnects, low k ILD, and 1 /spl mu/m/sup 2/ SRAM cell

  S. Thompson;N. Anand;M. Armstrong;C. Auth

  439
  Citations

• High performance 32nm logic technology featuring 2 nd generation high-k + metal gate transistors

  P. Packan;S. Akbar;M. Armstrong;D. Bergstrom

  286
  Citations

• A 32nm logic technology featuring 2 nd -generation high-k + metal-gate transistors, enhanced channel strain and 0.171μm 2 SRAM cell size in a 291Mb array

  S. Natarajan;M. Armstrong;M. Bost;R. Brain

  284
  Citations

• Transistor and manufacturing method thereof

  ティー． ボーア，マーク;T Bohr Mark;ガーニ，タヒル;Tahir Ghani

  277
  Citations

• In search of "Forever," continued transistor scaling one new material at a time

  S.E. Thompson;R.S. Chau;T. Ghani;K. Mistry

  271
  Citations

• Semiconductor device having doped epitaxial region and its methods of fabrication

  Anand S. Murthy;Daniel Bourne Aubertine;Tahir Ghani;Abhijit Jayant Pethe

  268
  Citations

• Scaling challenges and device design requirements for high performance sub-50 nm gate length planar CMOS transistors

  T. Ghani;K. Mistry;P. Packan;S. Thompson

  266
  Citations

• Effectiveness of reverse body bias for leakage control in scaled dual Vt CMOS ICs

  A. Keshavarzi;S. Ma;S. Narendra;B. Bloechel

  257
  Citations

• OPTIMIZATION OF MECHANICAL STRAIN IN CHANNELS OF P-MOS AND N-MOS TRANSISTORS

  Bohr Mark;Ghani Tahir;Cea Stephen;Mistry Kaizad

  231
  Citations

• III-V SEMICONDUCTOR DEVICE HAVING III-V SEMICONDUCTOR MATERIAL LAYER

  Glass Glenn A;Murthy Anand S;Ghani Tahir

  228
  Citations