Kevin Zhang mostly deals with Transistor, Electronic engineering, Electrical engineering, CMOS and Static random-access memory. His Transistor research incorporates themes from Optoelectronics and Logic gate. His Electronic engineering research focuses on Microprocessor and how it connects with Technology scaling, Interleaving and Characterization.
Kevin Zhang studies High voltage, a branch of Electrical engineering. His CMOS study combines topics from a wide range of disciplines, such as Low voltage, Virtual ground, Process variation and Integrated circuit. His Static random-access memory research is multidisciplinary, incorporating perspectives in Cache, Voltage and Leakage.
Kevin Zhang mainly focuses on Electronic engineering, Electrical engineering, CMOS, Static random-access memory and Transistor. His Electronic engineering study integrates concerns from other disciplines, such as Cache, Sense amplifier, Voltage and Electronic circuit. His Electrical engineering research focuses on subjects like Dram, which are linked to eDRAM and Amplifier.
His work carried out in the field of CMOS brings together such families of science as Analogue electronics, Soft error, Integrated injection logic and Node. Kevin Zhang has researched Static random-access memory in several fields, including Low voltage, Virtual ground, Memory cell and Integrated circuit. His work on PMOS logic as part of general Transistor study is frequently linked to Strained silicon, bridging the gap between disciplines.
His primary areas of investigation include CMOS, Electronic engineering, Electrical engineering, Transistor and Dram. CMOS and Static random-access memory are frequently intertwined in his study. His Electronic engineering study often links to related topics such as Power gating.
His work on Electrical engineering deals in particular with Low voltage, Electronic circuit and Voltage. His study in Transistor is interdisciplinary in nature, drawing from both Optoelectronics and Capacitor. His work deals with themes such as Sram cell and Fin width, which intersect with Optoelectronics.
Kevin Zhang mainly investigates Static random-access memory, CMOS, Transistor, Electronic circuit and Electrical engineering. His Static random-access memory study is concerned with Electronic engineering in general. His CMOS study typically links adjacent topics like Universal memory.
His work in the fields of Transistor, such as Sram cell and Fin width, overlaps with other areas such as Strained silicon. The study incorporates disciplines such as Dram and Leakage in addition to Electronic circuit. The concepts of his Optoelectronics study are interwoven with issues in Metal gate and Nanotechnology.
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A 3-GHz 70-mb SRAM in 65-nm CMOS technology with integrated column-based dynamic power supply
Kevin Zhang;U. Bhattacharya;Zhanping Chen;F. Hamzaoglu.
international solid-state circuits conference (2005)
Integrated nanoelectronics for the future
Robert Chau;Brian Doyle;Suman Datta;Jack Kavalieros.
Nature Materials (2007)
A 14nm logic technology featuring 2 nd -generation FinFET, air-gapped interconnects, self-aligned double patterning and a 0.0588 µm 2 SRAM cell size
S. Natarajan;M. Agostinelli;S. Akbar;M. Bost.
international electron devices meeting (2014)
A 65nm logic technology featuring 35nm gate lengths, enhanced channel strain, 8 Cu interconnect layers, low-k ILD and 0.57 /spl mu/m/sup 2/ SRAM cell
P. Bai;C. Auth;S. Balakrishnan;M. Bost.
international electron devices meeting (2004)
Characterization of multi-bit soft error events in advanced SRAMs
J. Maiz;S. Hareland;K. Zhang;P. Armstrong.
international electron devices meeting (2003)
SRAM design on 65-nm CMOS technology with dynamic sleep transistor for leakage reduction
K. Zhang;U. Bhattacharya;Zhanping Chen;F. Hamzaoglu.
IEEE Journal of Solid-state Circuits (2005)
High performance 32nm logic technology featuring 2 nd generation high-k + metal gate transistors
P. Packan;S. Akbar;M. Armstrong;D. Bergstrom.
international electron devices meeting (2009)
A 32nm logic technology featuring 2 nd -generation high-k + metal-gate transistors, enhanced channel strain and 0.171μm 2 SRAM cell size in a 291Mb array
S. Natarajan;M. Armstrong;M. Bost;R. Brain.
international electron devices meeting (2008)
A 4.6GHz 162Mb SRAM design in 22nm tri-gate CMOS technology with integrated active V MIN -enhancing assist circuitry
Eric Karl;Yih Wang;Yong-Gee Ng;Zheng Guo.
international solid-state circuits conference (2012)
Delaying forever: Uniaxial strained silicon transistors in a 90nm CMOS technology
K. Mistry;M. Armstrong;C. Auth;S. Cea.
symposium on vlsi technology (2004)
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