World's Best Scientists 2026 revealed!

D-Index & Metrics

Electronics and Electrical Engineering

D-Index
38
Citations
6713
World Ranking
4871
National Ranking
87

Overview

What is he best known for?

The fields of study he is best known for:

  • Electrical engineering
  • Integrated circuit
  • Transistor

Kevin Zhang mostly deals with Transistor, Electronic engineering, Electrical engineering, CMOS and Static random-access memory. His Transistor research incorporates themes from Optoelectronics and Logic gate. His Electronic engineering research focuses on Microprocessor and how it connects with Technology scaling, Interleaving and Characterization.

Kevin Zhang studies High voltage, a branch of Electrical engineering. His CMOS study combines topics from a wide range of disciplines, such as Low voltage, Virtual ground, Process variation and Integrated circuit. His Static random-access memory research is multidisciplinary, incorporating perspectives in Cache, Voltage and Leakage.

His most cited work include:

  • A 14nm logic technology featuring 2 nd -generation FinFET, air-gapped interconnects, self-aligned double patterning and a 0.0588 µm 2 SRAM cell size (374 citations)
  • A 3-GHz 70-mb SRAM in 65-nm CMOS technology with integrated column-based dynamic power supply (327 citations)
  • Integrated nanoelectronics for the future (294 citations)

What are the main themes of his work throughout his whole career to date?

Kevin Zhang mainly focuses on Electronic engineering, Electrical engineering, CMOS, Static random-access memory and Transistor. His Electronic engineering study integrates concerns from other disciplines, such as Cache, Sense amplifier, Voltage and Electronic circuit. His Electrical engineering research focuses on subjects like Dram, which are linked to eDRAM and Amplifier.

His work carried out in the field of CMOS brings together such families of science as Analogue electronics, Soft error, Integrated injection logic and Node. Kevin Zhang has researched Static random-access memory in several fields, including Low voltage, Virtual ground, Memory cell and Integrated circuit. His work on PMOS logic as part of general Transistor study is frequently linked to Strained silicon, bridging the gap between disciplines.

He most often published in these fields:

  • Electronic engineering (46.67%)
  • Electrical engineering (40.74%)
  • CMOS (32.59%)

What were the highlights of his more recent work (between 2012-2017)?

  • CMOS (32.59%)
  • Electronic engineering (46.67%)
  • Electrical engineering (40.74%)

In recent papers he was focusing on the following fields of study:

His primary areas of investigation include CMOS, Electronic engineering, Electrical engineering, Transistor and Dram. CMOS and Static random-access memory are frequently intertwined in his study. His Electronic engineering study often links to related topics such as Power gating.

His work on Electrical engineering deals in particular with Low voltage, Electronic circuit and Voltage. His study in Transistor is interdisciplinary in nature, drawing from both Optoelectronics and Capacitor. His work deals with themes such as Sram cell and Fin width, which intersect with Optoelectronics.

Between 2012 and 2017, his most popular works were:

  • A 14nm logic technology featuring 2 nd -generation FinFET, air-gapped interconnects, self-aligned double patterning and a 0.0588 µm 2 SRAM cell size (374 citations)
  • A 4.6 GHz 162 Mb SRAM Design in 22 nm Tri-Gate CMOS Technology With Integrated Read and Write Assist Circuitry (52 citations)
  • 13.1 A 1Gb 2GHz embedded DRAM in 22nm tri-gate CMOS technology (29 citations)

In his most recent research, the most cited papers focused on:

  • Electrical engineering
  • Integrated circuit
  • Transistor

Kevin Zhang mainly investigates Static random-access memory, CMOS, Transistor, Electronic circuit and Electrical engineering. His Static random-access memory study is concerned with Electronic engineering in general. His CMOS study typically links adjacent topics like Universal memory.

His work in the fields of Transistor, such as Sram cell and Fin width, overlaps with other areas such as Strained silicon. The study incorporates disciplines such as Dram and Leakage in addition to Electronic circuit. The concepts of his Optoelectronics study are interwoven with issues in Metal gate and Nanotechnology.

Best Publications

  • A 3-GHz 70-mb SRAM in 65-nm CMOS technology with integrated column-based dynamic power supply

    Kevin Zhang;U. Bhattacharya;Zhanping Chen;F. Hamzaoglu

  • A 14nm logic technology featuring 2 nd -generation FinFET, air-gapped interconnects, self-aligned double patterning and a 0.0588 µm 2 SRAM cell size

    S. Natarajan;M. Agostinelli;S. Akbar;M. Bost

  • Integrated nanoelectronics for the future

    Robert Chau;Brian Doyle;Suman Datta;Jack Kavalieros

  • A 65nm logic technology featuring 35nm gate lengths, enhanced channel strain, 8 Cu interconnect layers, low-k ILD and 0.57 /spl mu/m/sup 2/ SRAM cell

    P. Bai;C. Auth;S. Balakrishnan;M. Bost

  • Characterization of multi-bit soft error events in advanced SRAMs

    J. Maiz;S. Hareland;K. Zhang;P. Armstrong

  • SRAM design on 65-nm CMOS technology with dynamic sleep transistor for leakage reduction

    K. Zhang;U. Bhattacharya;Zhanping Chen;F. Hamzaoglu

  • High performance 32nm logic technology featuring 2 nd generation high-k + metal gate transistors

    P. Packan;S. Akbar;M. Armstrong;D. Bergstrom

  • A 32nm logic technology featuring 2 nd -generation high-k + metal-gate transistors, enhanced channel strain and 0.171μm 2 SRAM cell size in a 291Mb array

    S. Natarajan;M. Armstrong;M. Bost;R. Brain

  • A 4.6GHz 162Mb SRAM design in 22nm tri-gate CMOS technology with integrated active V MIN -enhancing assist circuitry

    Eric Karl;Yih Wang;Yong-Gee Ng;Zheng Guo

  • Delaying forever: Uniaxial strained silicon transistors in a 90nm CMOS technology

    K. Mistry;M. Armstrong;C. Auth;S. Cea

  • Erratic fluctuations of sram cache vmin at the 90nm process technology node

    M. Agostinelli;J. Hicks;J. Xu;B. Woolery

  • A 1.1 GHz 12 $\mu$ A/Mb-Leakage SRAM Design in 65 nm Ultra-Low-Power CMOS Technology With Integrated Leakage Reduction for Mobile Applications

    Yih Wang;Hong Jo Ahn;U. Bhattacharya;Zhanping Chen

  • A 32nm SoC platform technology with 2 nd generation high-k/metal gate transistors optimized for ultra low power, high performance, and high density product applications

    C.-H. Jan;M. Agostinelli;M. Buehler;Z.-P. Chen

  • Wordline & Bitline Pulsing Schemes for Improving SRAM Cell Stability in Low-Vcc 65nm CMOS Designs

    M. Khellah;Y. Ye;N. Kim;D. Somasekhar

  • Multi-Phase 1 GHz Voltage Doubler Charge Pump in 32 nm Logic Process

    D. Somasekhar;B. Srinivasan;G. Pandya;F. Hamzaoglu

  • Dual-V/sub T/ SRAM cells with full-swing single-ended bit line sensing for high-performance on-chip cache in 0.13 /spl mu/m technology generation

    Fatih Hamzaoglu;Yibin Te;Ali Keshavarzi;Kevin Zhang

  • SRAM design on 65nm CMOS technology with integrated leakage reduction scheme

    K. Zhang;U. Bhattacharya;Z. Chen;F. Hamzaoglu

  • A 3.8 GHz 153 Mb SRAM Design With Dynamic Stability Enhancement and Leakage Reduction in 45 nm High-k Metal Gate CMOS Technology

    F. Hamzaoglu;K. Zhang;Yih Wang;H.J. Ahn

  • A 4.0 GHz 291Mb voltage-scalable SRAM design in 32nm high-κ metal-gate CMOS with integrated power management

    Y. Wang;U. Bhattacharya;F. Hamzaoglu;P. Kolar

  • A 32 nm High-k Metal Gate SRAM With Adaptive Dynamic Stability Enhancement for Low-Voltage Operation

    Hyunwoo Nho;Pramod Kolar;Fatih Hamzaoglu;Yih Wang

Frequent Co-Authors

Fatih Hamzaoglu
Fatih Hamzaoglu Intel (United States)
Dinesh Somasekhar
Dinesh Somasekhar Intel (United States)
Vivek De
Vivek De Intel (United States)
Muhammad M. Khellah
Muhammad M. Khellah Intel (United States)
Nam Sung Kim
Nam Sung Kim University of Illinois at Urbana-Champaign
Mark T. Bohr
Mark T. Bohr Intel (United States)
Tahir Ghani
Tahir Ghani Intel (United States)
Tanay Karnik
Tanay Karnik Intel (United States)
Ali Keshavarzi
Ali Keshavarzi Stanford University
Brian S. Doyle
Brian S. Doyle Intel (United States)

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