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Muhammad M. Khellah

Muhammad M. Khellah

D-Index & Metrics

Electronics and Electrical Engineering

D-Index
36
Citations
5322
World Ranking
5352
National Ranking
1848

Overview

Muhammad M. Khellah is affiliated with Intel in the United States. Their research primarily spans the fields of engineering and computer science, with a focus on electrical and electronic engineering, hardware and architecture, and computer networks and communications.

The scientist's work covers a range of topics related to semiconductor materials and devices, parallel computing and optimization techniques, advanced data storage technologies, advanced memory and neural computing, low-power high-performance VLSI design, electrostatic discharge in electronics, and radiation effects in electronics.

Recent papers authored or co-authored by Muhammad M. Khellah include:

  • Advances in Microprocessor Cache Architectures Over the Last 25 Years, 2021, IEEE Micro
  • An All-Digital, VMAX-Compliant, Stable, and Scalable Distributed Charge Injection Scheme in 10-nm CMOS for Fast and Local Mitigation of Voltage Droop, 2020, IEEE Journal of Solid-State Circuits
  • A Back-Sampling Chain Technique for Accelerated Detection, Characterization, and Reconstruction of Radiation-Induced Transient Pulses, 2021, IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Their frequent co-authors include:

  • Vivek De
  • Minki Cho
  • Andres Malavasi
  • James Tschanz
  • Ravi Iyer

Muhammad M. Khellah publishes regularly in several scholarly venues, notably:

  • IEEE Micro
  • IEEE Journal of Solid-State Circuits
  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Best Publications

  • Trading off Cache Capacity for Reliability to Enable Low Voltage Operation

    Chris Wilkerson;Hongliang Gao;Alaa R. Alameldeen;Zeshan Chishti

  • A 45 nm Resilient Microprocessor Core for Dynamic Variation Tolerance

    K A Bowman;J W Tschanz;S L Lu;P A Aseron

  • Floating-body dynamic random access memory and method of fabrication in tri-gate technology

    Stephen H. Tang;Ali Keshavarzi;Dinesh Somasekhar;Fabrice Paillet

  • Wordline & Bitline Pulsing Schemes for Improving SRAM Cell Stability in Low-Vcc 65nm CMOS Designs

    M. Khellah;Y. Ye;N. Kim;D. Somasekhar

  • Floating-body memory cell write

    Stephen H. Tang;Ali Keshavarzi;Dinesh Somasekhar;Fabrice Paillet

  • Multi-Phase 1 GHz Voltage Doubler Charge Pump in 32 nm Logic Process

    D. Somasekhar;B. Srinivasan;G. Pandya;F. Hamzaoglu

  • Floating-body dram using write word line for increased retention time

    Stephen Tang;Ali Keshavarzi;Dinesh Somasekhar;Fabrice Paillet

  • OTP antifuse cell and cell array

    Fabrice Paillet;Ali Keshavarzi;Muhammad M. Khellah;Dinesh Somasekhar

  • Floating-body dynamic random access memory with purge line

    Stephen H. Tang;Ali Keshavarzi;Dinesh Somasekhar;Fabrice Paillet

  • Method and apparatus to generate a reference value in a memory array

    Dinesh Somasekhar;Yibin Ye;Muhammad M. Khellah;Fabrice Paillet

  • Purge-based floating body memory

    Ali Keshavarzi;Stephen H Tang;Dinesh Somasekhar;Fabrice Paillet

  • A 0.45–1 V Fully-Integrated Distributed Switched Capacitor DC-DC Converter With High Density MIM Capacitor in 22 nm Tri-Gate CMOS

    Rinkle Jain;Bibiche M. Geuskens;Stephen T. Kim;Muhammad M. Khellah

  • Floating-body DRAM with two-phase write

    Stephen H. Tang;Ali Keshavarzi;Dinesh Somasekhar;Fabrice Paillet

  • 2 GHz 2 Mb 2T Gain Cell Memory Macro With 128 GBytes/sec Bandwidth in a 65 nm Logic Process Technology

    D. Somasekhar;Yibin Ye;P. Aseron;Shih-Lien Lu

  • Accurate Estimation of SRAM Dynamic Stability

    D.E. Khalil;M. Khellah;Nam-Sung Kim;Y. Ismail

  • Serial-Link Bus: A Low-Power On-Chip Bus Architecture

    M. Ghoneima;Y. Ismail;M.M. Khellah;J. Tschanz

  • SRAM array with dynamic voltage for reducing active leakage power

    Muhammad Khellah;Vivek De;Dinesh Somasekhar;Yibin Ye

  • Formal derivation of optimal active shielding for low-power on-chip buses

    M. Ghoneima;Y.I. Ismail;M.M. Khellah;J.W. Tschanz

  • Enabling Wide Autonomous DVFS in a 22 nm Graphics Execution Core Using a Digitally Controlled Fully Integrated Voltage Regulator

    Stephen T. Kim;Yi-Chun Shih;Kaushik Mazumdar;Rinkle Jain

  • PVT-and-aging adaptive wordline boosting for 8T SRAM power reduction

    Arijit Raychowdhury;Bibiche Geuskens;Jaydeep Kulkarni;Jim Tschanz

  • A 45nm resilient and adaptive microprocessor core for dynamic variation tolerance

    James Tschanz;Keith Bowman;Shih-Lien Lu;Paolo Aseron

Frequent Co-Authors

Vivek De
Vivek De Intel (United States)
James W. Tschanz
James W. Tschanz Intel (United States)
Dinesh Somasekhar
Dinesh Somasekhar Intel (United States)
Tanay Karnik
Tanay Karnik Intel (United States)
Ali Keshavarzi
Ali Keshavarzi Stanford University
Shih-Lien Lu
Shih-Lien Lu Washington State University
Yehea Ismail
Yehea Ismail American University in Cairo
Nam Sung Kim
Nam Sung Kim University of Illinois at Urbana-Champaign
Arijit Raychowdhury
Arijit Raychowdhury Georgia Institute of Technology
Keith Bowman
Keith Bowman Qualcomm (United States)

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