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Research.com Recognitions

  • 2016 - IEEE Fellow For contributions to low-voltage microarchitecture and approximate computing

Overview

Shih-Lien Lu is affiliated with Washington State University in the United States. The scientist's work has been recognized in the field of computer engineering, particularly in microarchitecture and approximate computing.

In 2016, Shih-Lien Lu was named an IEEE Fellow for contributions to low-voltage microarchitecture and approximate computing. This award marks a significant recognition within the engineering community.

Best Publications

  • Energy-Efficient and Metastability-Immune Resilient Circuits for Dynamic Variation Tolerance

    Keith A. Bowman;James W. Tschanz;Nam Sung Kim;Janice C. Lee

  • Trading off Cache Capacity for Reliability to Enable Low Voltage Operation

    Chris Wilkerson;Hongliang Gao;Alaa R. Alameldeen;Zeshan Chishti

  • A 45 nm Resilient Microprocessor Core for Dynamic Variation Tolerance

    K A Bowman;J W Tschanz;S L Lu;P A Aseron

  • Floating-body dynamic random access memory and method of fabrication in tri-gate technology

    Stephen H. Tang;Ali Keshavarzi;Dinesh Somasekhar;Fabrice Paillet

  • Technology comparison for large last-level caches (L 3 Cs): Low-leakage SRAM, low write-energy STT-RAM, and refresh-optimized eDRAM

    Mu-Tien Chang;P. Rosenfeld;Shih-Lien Lu;B. Jacob

  • Reducing cache power with low-cost, multi-bit error-correcting codes

    Chris Wilkerson;Alaa R. Alameldeen;Zeshan Chishti;Wei Wu

  • Improving cache lifetime reliability at ultra-low voltages

    Zeshan Chishti;Alaa R. Alameldeen;Chris Wilkerson;Wei Wu

  • Energy-efficient cache design using variable-strength error-correcting codes

    Alaa R. Alameldeen;Ilya Wagner;Zeshan Chishti;Wei Wu

  • Circuit techniques for dynamic variation tolerance

    Keith Bowman;James Tschanz;Chris Wilkerson;Shih-Lien Lu

  • DRAM Refresh Mechanisms, Penalties, and Trade-Offs

    Ishwar Bhati;Mu-Tien Chang;Zeshan Chishti;Shih-Lien Lu

  • Floating-body memory cell write

    Stephen H. Tang;Ali Keshavarzi;Dinesh Somasekhar;Fabrice Paillet

  • Open bit line DRAM and method for reducing noise for open bit line DRAM operation

    Dinesh Somasekhar;Lu Shih-Lien L;De Vivek K

  • Low-leakage MOS planar capacitors for use within DRAM storage cells

    Dinesh Somasekhar;Shih-Lien L. Lu;Vivek K. De

  • One-transistor and one-capacitor DRAM cell for logic process technology

    Shih-Lien L. Lu;Vivek K. De

  • Floating-body dynamic random access memory with purge line

    Stephen H. Tang;Ali Keshavarzi;Dinesh Somasekhar;Fabrice Paillet

  • Method and apparatus to generate a reference value in a memory array

    Dinesh Somasekhar;Yibin Ye;Muhammad M. Khellah;Fabrice Paillet

  • Flexible auto-refresh: enabling scalable and energy-efficient DRAM refresh reductions

    Ishwar Bhati;Zeshan Chishti;Shih-Lien Lu;Bruce Jacob

  • Floating-body DRAM with two-phase write

    Stephen H. Tang;Ali Keshavarzi;Dinesh Somasekhar;Fabrice Paillet

  • Energy-Efficient and Metastability-Immune Timing-Error Detection and Instruction-Replay-Based Recovery Circuits for Dynamic-Variation Tolerance

    K.A. Bowman;J.W. Tschanz;Nam Sung Kim;J.C. Lee

  • Novel FPGA based Haar classifier face detection algorithm acceleration

    Changjian Gao;Shih-Lien Lu

Frequent Co-Authors

Vivek De
Vivek De Intel (United States)
Dinesh Somasekhar
Dinesh Somasekhar Intel (United States)
Muhammad M. Khellah
Muhammad M. Khellah Intel (United States)
James W. Tschanz
James W. Tschanz Intel (United States)
Tanay Karnik
Tanay Karnik Intel (United States)
Keith Bowman
Keith Bowman Qualcomm (United States)
Ali Keshavarzi
Ali Keshavarzi Stanford University
Arijit Raychowdhury
Arijit Raychowdhury Georgia Institute of Technology
Ram Krishnamurthy
Ram Krishnamurthy Intel (United States)
Nam Sung Kim
Nam Sung Kim University of Illinois at Urbana-Champaign

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