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D-Index & Metrics

Electronics and Electrical Engineering

D-Index
31
Citations
5111
World Ranking
6495
National Ranking
2128

Overview

Keith Bowman is affiliated with Qualcomm in the United States. Their research primarily focuses on engineering, with a strong emphasis on electrical and electronic engineering as well as biomedical engineering.

Bowman has an extensive publication record in the field of electrical and electronic engineering, contributing to various subfields and topics including:

  • Low-power high-performance VLSI design
  • Semiconductor materials and devices
  • Advancements in Semiconductor Devices and Circuit Design
  • Analog and Mixed-Signal Circuit Design
  • Advanced Memory and Neural Computing
  • Smart Grid Energy Management
  • 3D IC and TSV technologies

Their recent publications cover a range of relevant topics and were published in notable venues between 2020 and 2022. Key papers include:

  • "Review, Survey, and Benchmark of Recent Digital LDO Voltage Regulators," 2022, 2022 IEEE Custom Integrated Circuits Conference (CICC)
  • "A Proactive System for Voltage-Droop Mitigation in a 7-nm Hexagon™ Processor," 2020, IEEE Journal of Solid-State Circuits
  • "A Current and Temperature Limiting System in a 7-nm Hexagon™ Compute Digital Signal Processor," 2021, IEEE Journal of Solid-State Circuits
  • "Constructive Feedback, Positive Influence [People]," 2021, IEEE Solid-State Circuits Magazine
  • "ISSCC Special Event: Going Remote-Challenges and Opportunities for Remote Learning, Work, and Collaboration [Conferece Reports]," 2021, IEEE Solid-State Circuits Magazine

Keith Bowman's frequent coauthors include:

  • Vijay Kiran Kalyanam
  • Eric Mahurin
  • Jacob A. Abraham
  • Zhaoqing Wang
  • Sung Justin Kim

The venues where Bowman's research appears most frequently are:

  • IEEE Journal of Solid-State Circuits
  • IEEE Solid-State Circuits Magazine
  • 2022 IEEE Custom Integrated Circuits Conference (CICC)
  • IEEE Spectrum

Best Publications

  • Impact of die-to-die and within-die parameter fluctuations on the maximum clock frequency distribution for gigascale integration

    K.A. Bowman;S.G. Duvall;J.D. Meindl

  • Energy-Efficient and Metastability-Immune Resilient Circuits for Dynamic Variation Tolerance

    Keith A. Bowman;James W. Tschanz;Nam Sung Kim;Janice C. Lee

  • Energy-Efficient and Metastability-Immune Resilient Circuits for Dynamic Variation Tolerance

    K.A. Bowman;J.W. Tschanz;Nam Sung Kim;J.C. Lee

  • A physical alpha-power law MOSFET model

    K.A. Bowman;B.L. Austin;J.C. Eble;Xinghai Tang

  • A 45 nm Resilient Microprocessor Core for Dynamic Variation Tolerance

    K A Bowman;J W Tschanz;S L Lu;P A Aseron

  • A physical alpha-power law MOSFET model

    Keith A. Bowman;Blanca L. Austin;John C. Eble;Xinghai Tang

  • Tunable replica circuits and adaptive voltage-frequency techniques for dynamic voltage, temperature, and aging variation tolerance

    James Tschanz;Keith Bowman;Steve Walstra;Marty Agostinelli

  • Within-Die Variation-Aware Dynamic-Voltage-Frequency-Scaling With Optimal Core Allocation and Thread Hopping for the 80-Core TeraFLOPS Processor

    S Dighe;S R Vangal;P Aseron;S Kumar

  • Impact of Parameter Variations on Circuits and Microarchitecture

    O.S. Unsal;J.W. Tschanz;K. Bowman;V. De

  • Circuit techniques for dynamic variation tolerance

    Keith Bowman;James Tschanz;Chris Wilkerson;Shih-Lien Lu

  • Impact of extrinsic and intrinsic parameter fluctuations on CMOS circuit performance

    K.A. Bowman;Xinghai Tang;J.C. Eble;J.D. Menldl

  • Energy-Efficient and Metastability-Immune Timing-Error Detection and Instruction-Replay-Based Recovery Circuits for Dynamic-Variation Tolerance

    K.A. Bowman;J.W. Tschanz;Nam Sung Kim;J.C. Lee

  • A minimum total power methodology for projecting limits on CMOS GSI

    A.J. Bhavnagarwala;B.L. Austin;K.A. Bowman;J.D. Meindl

  • Variation-tolerant circuits: circuit solutions and techniques

    Jim Tschanz;Keith Bowman;Vivek De

  • Optimal n-tier multilevel interconnect architectures for gigascale integration (GSI)

    R. Venkatesan;J.A. Davis;K.A. Bowman;J.D. Meindl

  • PVT-and-aging adaptive wordline boosting for 8T SRAM power reduction

    Arijit Raychowdhury;Bibiche Geuskens;Jaydeep Kulkarni;Jim Tschanz

  • A 22 nm All-Digital Dynamically Adaptive Clock Distribution for Supply Voltage Droop Tolerance

    K. A. Bowman;C. Tokunaga;T. Karnik;V. K. De

  • Impact of Die-to-Die and Within-Die Parameter Variations on the Clock Frequency and Throughput of Multi-Core Processors

    K.A. Bowman;A.R. Alameldeen;S.T. Srinivasan;C.B. Wilkerson

  • Impact of die-to-die and within-die parameter variations on the throughput distribution of multi-core processors

    Keith A. Bowman;Alaa R. Alameldeen;Srikanth T. Srinivasan;Chris B. Wilkerson

  • A 45nm resilient and adaptive microprocessor core for dynamic variation tolerance

    James Tschanz;Keith Bowman;Shih-Lien Lu;Paolo Aseron

  • Within-die variation-aware dynamic-voltage-frequency scaling core mapping and thread hopping for an 80-core processor

    Saurabh Dighe;Sriram Vangal;Paolo Aseron;Shasi Kumar

  • Variation -To I era n t C i rcu its : C i rc u i t So I uti o n s and Techniques

    Jim Tschanz;Keith Bowman;Vivek De

Frequent Co-Authors

James W. Tschanz
James W. Tschanz Intel (United States)
Vivek De
Vivek De Intel (United States)
Tanay Karnik
Tanay Karnik Intel (United States)
Shih-Lien Lu
Shih-Lien Lu Washington State University
James D. Meindl
James D. Meindl Georgia Institute of Technology
Arijit Raychowdhury
Arijit Raychowdhury Georgia Institute of Technology
Muhammad M. Khellah
Muhammad M. Khellah Intel (United States)
Nam Sung Kim
Nam Sung Kim University of Illinois at Urbana-Champaign
Shekhar Borkar
Shekhar Borkar Qualcomm (United States)
Jacob A. Abraham
Jacob A. Abraham The University of Texas at Austin

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