H-Index & Metrics Top Publications

H-Index & Metrics

Discipline name H-index Citations Publications World Ranking National Ranking
Electronics and Electrical Engineering H-index 50 Citations 8,673 226 World Ranking 1188 National Ranking 546

Research.com Recognitions

Awards & Achievements

2018 - Semiconductor Industry Association University Researcher Award

2006 - IEEE Fellow For development of a communication-centric design paradigm for low power systems on a chip.

Overview

What is he best known for?

The fields of study he is best known for:

  • Electrical engineering
  • Algorithm
  • Telecommunications

Electronic engineering, Algorithm, Parallel computing, Low-power electronics and Signal processing are his primary areas of study. His research in Electronic engineering intersects with topics in Electronic circuit and Error detection and correction. His biological study spans a wide range of topics, including Stochastic process, Theoretical computer science, Reliability and Deep neural networks.

His Parallel computing study combines topics from a wide range of disciplines, such as Concatenated error correction code, Chip and Decoding methods, Low-density parity-check code, Turbo code. His Low-power electronics study integrates concerns from other disciplines, such as Transmitter, Radio receiver and Efficient energy use, Electrical engineering. His Signal processing study also includes fields such as

  • Filter which is related to area like Digital signal processor, Digital signal processing, Digital filter and Adaptive filter,
  • Reduction which connect with Analog signal processing.

His most cited work include:

  • High-throughput LDPC decoders (551 citations)
  • High-speed architectures for Reed-Solomon decoders (277 citations)
  • Soft digital signal processing (239 citations)

What are the main themes of his work throughout his whole career to date?

Naresh R. Shanbhag mainly focuses on Electronic engineering, Algorithm, CMOS, Efficient energy use and Signal processing. His Electronic engineering study incorporates themes from Electronic circuit, Electrical engineering and Bit error rate. In general Algorithm study, his work on Decoding methods, Reduction and Error detection and correction often relates to the realm of Block, thereby connecting several areas of interest.

His CMOS research includes elements of Inverter, Voltage, Logic gate, Low-power electronics and Coding. Computation and Computer engineering is closely connected to Robustness in his research, which is encompassed under the umbrella topic of Efficient energy use. Naresh R. Shanbhag interconnects Adaptive filter, Overhead, Energy and Filter in the investigation of issues within Signal processing.

He most often published in these fields:

  • Electronic engineering (42.77%)
  • Algorithm (21.97%)
  • CMOS (19.94%)

What were the highlights of his more recent work (between 2014-2021)?

  • Efficient energy use (15.32%)
  • Algorithm (21.97%)
  • Artificial intelligence (6.65%)

In recent papers he was focusing on the following fields of study:

Naresh R. Shanbhag mainly investigates Efficient energy use, Algorithm, Artificial intelligence, CMOS and Static random-access memory. His Efficient energy use research is multidisciplinary, incorporating elements of Mixed-signal integrated circuit, Energy consumption, Real-time computing, Instruction set and Robustness. The Algorithm study combines topics in areas such as Fixed point, Energy and Convolutional neural network.

He focuses mostly in the field of Artificial intelligence, narrowing it down to topics relating to Estimator and, in certain cases, Signal processing. Naresh R. Shanbhag is researching CMOS as part of the investigation of Electrical engineering and Electronic engineering. His Electronic engineering study frequently draws connections between adjacent fields such as Analog-to-digital converter.

Between 2014 and 2021, his most popular works were:

  • Binodal, wireless epidermal electronic systems with in-sensor analytics for neonatal intensive care (172 citations)
  • A 42pJ/decision 3.12TOPS/W robust in-memory machine learning classifier with on-chip training (80 citations)
  • A Multi-Functional In-Memory Inference Processor Using a Standard 6T SRAM Array (48 citations)

In his most recent research, the most cited papers focused on:

  • Algorithm
  • Electrical engineering
  • Telecommunications

Naresh R. Shanbhag mostly deals with Efficient energy use, Algorithm, Static random-access memory, Random access memory and Artificial neural network. His work carried out in the field of Efficient energy use brings together such families of science as Energy consumption, Machine learning, Convolutional neural network, CMOS and Robustness. His CMOS study introduces a deeper knowledge of Electronic engineering.

His research investigates the connection between Algorithm and topics such as Fixed point that intersect with issues in Upper and lower bounds, Quantization and Feed forward. His study in Static random-access memory is interdisciplinary in nature, drawing from both Learning classifier system, Analog signal processing, Computer engineering and Parallel computing. As a part of the same scientific study, Naresh R. Shanbhag usually deals with the Random access memory, concentrating on Computational science and frequently concerns with Memory architecture, Magnetoresistive random-access memory, Integrated circuit and Matched filter.

This overview was generated by a machine learning system which analysed the scientist’s body of work. If you have any feedback, you can contact us here.

Top Publications

High-throughput LDPC decoders

M.M. Mansour;N.R. Shanbhag.
IEEE Transactions on Very Large Scale Integration Systems (2003)

733 Citations

High-speed architectures for Reed-Solomon decoders

D.V. Sarwate;N.R. Shanbhag.
IEEE Transactions on Very Large Scale Integration Systems (2001)

444 Citations

Soft-Error-Rate-Analysis (SERA) Methodology

Ming Zhang;N.R. Shanbhag.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (2006)

339 Citations

Soft digital signal processing

R. Hegde;N.R. Shanbhag.
IEEE Transactions on Very Large Scale Integration Systems (2001)

327 Citations

A 640-Mb/s 2048-bit programmable LDPC decoder chip

M.M. Mansour;N.R. Shanbhag.
IEEE Journal of Solid-state Circuits (2006)

305 Citations

A coding framework for low-power address and data busses

S. Ramprasad;N.R. Shanbhag;I.N. Hajj.
IEEE Transactions on Very Large Scale Integration Systems (1999)

282 Citations

Energy-efficient signal processing via algorithmic noise-tolerance

Rajamohana Hegde;Naresh R. Shanbhag.
international symposium on low power electronics and design (1999)

281 Citations

Sequential Element Design With Built-In Soft Error Resilience

Ming Zhang;S. Mitra;T.M. Mak;N. Seifert.
IEEE Transactions on Very Large Scale Integration Systems (2006)

269 Citations

Coding for system-on-chip networks: a unified framework

S.R. Sridhara;N.R. Shanbhag.
IEEE Transactions on Very Large Scale Integration Systems (2005)

264 Citations

Low-power VLSI decoder architectures for LDPC codes

Mohammad M. Mansour;Naresh R. Shanbhag.
international symposium on low power electronics and design (2002)

262 Citations

Profile was last updated on December 6th, 2021.
Research.com Ranking is based on data retrieved from the Microsoft Academic Graph (MAG).
The ranking h-index is inferred from publications deemed to belong to the considered discipline.

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