Tong Zhang focuses on Decoding methods, Low-density parity-check code, Electronic engineering, Parallel computing and Flash memory. His Soft-decision decoder and Block code study, which is part of a larger body of work in Decoding methods, is frequently linked to Throughput, bridging the gap between disciplines. His Low-density parity-check code study combines topics in areas such as Quantization, Error detection and correction, Computer engineering and Concatenated error correction code.
His Electronic engineering research incorporates themes from Spatial multiplexing, MIMO, QAM and Detector. His Parallel computing research includes themes of Encoder and Encoding. Tong Zhang combines subjects such as Systems modeling, BCH code and Memory cell with his study of Flash memory.
Tong Zhang mainly focuses on Electronic engineering, Computer hardware, Decoding methods, Low-density parity-check code and Embedded system. His study in the fields of CMOS under the domain of Electronic engineering overlaps with other disciplines such as Throughput. The concepts of his Computer hardware study are interwoven with issues in Nand flash memory and Error detection and correction.
His studies deal with areas such as Computer engineering and Parallel computing as well as Decoding methods. His research integrates issues of Forward error correction, Communication channel and Concatenated error correction code in his study of Low-density parity-check code. His Embedded system research incorporates elements of Dram, CPU cache, Non-volatile memory, Static random-access memory and Overhead.
The scientist’s investigation covers issues in Embedded system, Flash memory, Computer hardware, Latency and Dram. His Embedded system research is multidisciplinary, relying on both Supercomputer and Computer data storage. His Flash memory research includes elements of Data compression, Flash file system and Cache.
His biological study spans a wide range of topics, including Energy consumption, Nand flash memory and Integrated circuit. His study in Redundancy is interdisciplinary in nature, drawing from both Decoding methods and CAS latency. The study incorporates disciplines such as Electronic engineering and Communication channel in addition to Block.
His scientific interests lie mostly in Flash memory, Computer hardware, Latency, Embedded system and Computer data storage. Tong Zhang has researched Flash memory in several fields, including Scalability, Cache, Flash file system and Universal memory, Interleaved memory. His Computer hardware research is multidisciplinary, incorporating perspectives in Nand flash memory and Integrated circuit.
His research investigates the link between Latency and topics such as Efficient energy use that cross with problems in Decoding methods. His Decoding methods study typically links adjacent topics like Energy consumption. The Computer data storage study combines topics in areas such as Semiconductor memory, Error detection and correction and Transcoding.
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On the Use of Soft-Decision Error-Correction Codes in nand Flash Memory
Guiqiang Dong;Ningde Xie;Tong Zhang.
IEEE Transactions on Circuits and Systems I-regular Papers (2011)
Block-LDPC: a practical LDPC coding system design approach
Hao Zhong;Tong Zhang.
IEEE Transactions on Circuits and Systems I-regular Papers (2005)
LDPC-in-SSD: making advanced error correction codes work effectively in solid state drives
Kai Zhao;Wenzhe Zhao;Hongbin Sun;Tong Zhang.
file and storage technologies (2013)
Design of VLSI implementation-oriented LDPC codes
Hao Zhong;Tong Zhang.
vehicular technology conference (2003)
A 54 Mbps (3,6)-regular FPGA LDPC decoder
Tong Zhang;K.K. Parhi.
signal processing systems (2002)
Relaxed $K$ -Best MIMO Signal Detector Design and VLSI Implementation
Sizhong Chen;Tong Zhang;Yan Xin.
IEEE Transactions on Very Large Scale Integration Systems (2007)
Using Data Postcompensation and Predistortion to Tolerate Cell-to-Cell Interference in MLC nand Flash Memory
Guiqiang Dong;Shu Li;Tong Zhang.
IEEE Transactions on Circuits and Systems I-regular Papers (2010)
On finite precision implementation of low density parity check codes decoder
T. Zhang;Z. Wang;K.K. Parhi.
international symposium on circuits and systems (2001)
Design of Last-Level On-Chip Cache Using Spin-Torque Transfer RAM (STT RAM)
Wei Xu;Hongbin Sun;Xiaobin Wang;Yiran Chen.
IEEE Transactions on Very Large Scale Integration Systems (2011)
VLSI implementation-oriented (3, k)-regular low-density parity-check codes
Tong Zhang;K.K. Parhi.
signal processing systems (2001)
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