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D-Index & Metrics

Electronics and Electrical Engineering

D-Index
40
Citations
10939
World Ranking
4397
National Ranking
1564

Overview

Naveen Verma is affiliated with Princeton University in the United States. Their research primarily spans the field of engineering, with a strong concentration in electrical and electronic engineering. Their work also covers mechanical engineering, biomedical engineering, artificial intelligence, and computer vision and pattern recognition.

Their research topics include advanced memory and neural computing, ferroelectric and negative capacitance devices, advanced materials and mechanics, soft robotics and applications, advanced neural network applications, micro and nano robotics, and structural health monitoring techniques.

Frequent coauthors collaborating with Naveen Verma include S. Wagner, James C. Sturm, Prakhar Kumar, Peter Deaville, and Zhiwu Zheng.

Verma has contributed to multiple publication venues, primarily:

  • IEEE Journal of Solid-State Circuits
  • IEEE Transactions on Circuits and Systems I Regular Papers
  • arXiv (Cornell University)
  • 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)
  • IEEE Transactions on Robotics

Notable recent papers authored or coauthored by Naveen Verma include:

  • "A Programmable Heterogeneous Microprocessor Based on Bit-Scalable In-Memory Computing", 2020, IEEE Journal of Solid-State Circuits
  • "Scalable and Programmable Neural Network Inference Accelerator Based on In-Memory Computing", 2021, IEEE Journal of Solid-State Circuits
  • "A 22nm 128-kb MRAM Row/Column-Parallel In-Memory Computing Macro with Memory-Resistance Boosting and Multi-Column ADC Readout", 2022, 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)
  • "Large-Area Resistive Strain Sensing Sheet for Structural Health Monitoring", 2020, Sensors
  • "A phased array based on large-area electronics that operates at gigahertz frequency", 2021, Nature Electronics

Best Publications

  • Graphene-based wireless bacteria detection on tooth enamel

    Manu Sebastian Mannoor;Hu Tao;Jefferson D. Clayton;Amartya Sengupta

  • 3D printed bionic ears.

    Manu S. Mannoor;Ziwen Jiang;Teena James;Yong Lin Kong

  • A Micro-Power EEG Acquisition SoC With Integrated Feature Extraction Processor for a Chronic Seizure Detection System

    Naveen Verma;Ali Shoeb;Jose Bohorquez;Joel Dawson

  • A 256 kb 65 nm 8T Subthreshold SRAM Employing Sense-Amplifier Redundancy

    N. Verma;A.P. Chandrakasan

  • In-Memory Computation of a Machine-Learning Classifier in a Standard 6T SRAM Array

    Jintao Zhang;Zhuo Wang;Naveen Verma

  • A 65 nm Sub- $V_{t}$ Microcontroller With Integrated SRAM and Switched Capacitor DC-DC Converter

    J. Kwong;Y.K. Ramadass;N. Verma;A.P. Chandrakasan

  • An Ultra Low Energy 12-bit Rate-Resolution Scalable SAR ADC for Wireless Sensor Nodes

    N. Verma;A.P. Chandrakasan

  • In-Memory Computing: Advances and prospects

    Naveen Verma;Hongyang Jia;Hossein Valavi;Yinqi Tang

  • Ultralow-Power Electronics for Biomedical Applications

    Anantha P Chandrakasan;Naveen Verma;Denis C Daly

  • Design considerations for ultra-low energy wireless microsensor nodes

    B.H. Calhoun;D.C. Daly;Naveen Verma;D.F. Finchelstein

  • A 64-Tile 2.4-Mb In-Memory-Computing CNN Accelerator Employing Charge-Domain Compute

    Hossein Valavi;Peter J. Ramadge;Eric Nestler;Naveen Verma

  • A 65nm 8T Sub-Vt SRAM Employing Sense-Amplifier Redundancy

    Naveen Verma;A.P. Chandrakasan

  • Nanometer MOSFET Variation in Minimum Energy Subthreshold Circuits

    N. Verma;J. Kwong;A.P. Chandrakasan

  • A 65nm Sub-V t Microcontroller with Integrated SRAM and Switched-Capacitor DC-DC Converter

    J. Kwong;Y. Ramadass;N. Verma;M. Koesler

  • A Low-Power Processor With Configurable Embedded Machine-Learning Accelerators for High-Order and Adaptive Analysis of Medical-Sensor Signals

    Kyong Ho Lee;N. Verma

  • A Programmable Heterogeneous Microprocessor Based on Bit-Scalable In-Memory Computing

    Hongyang Jia;Hossein Valavi;Yinqi Tang;Jintao Zhang

  • A machine-learning classifier implemented in a standard 6T SRAM array

    Jintao Zhang;Zhuo Wang;Naveen Verma

  • A Reconfigurable 8T Ultra-Dynamic Voltage Scalable (U-DVS) SRAM in 65 nm CMOS

    M.E. Sinangil;N. Verma;A.P. Chandrakasan

  • A Programmable Neural-Network Inference Accelerator Based on Scalable In-Memory Computing

    Hongyang Jia;Murat Ozatay;Yinqi Tang;Hossein Valavi

  • A 25/spl mu/W 100kS/s 12b ADC for wireless micro-sensor applications

    N. Verma;A.P. Chandrakasan

  • A Mixed-Signal Binarized Convolutional-Neural-Network Accelerator Integrating Dense Weight Storage and Multiplication for Reduced Data Movement

    Hossein Valavi;Peter J. Ramadge;Eric Nestler;Naveen Verma

  • Technologies for Ultradynamic Voltage Scaling

    A.P. Chandrakasan;D.C. Daly;D.F. Finchelstein;J. Kwong

Frequent Co-Authors

James C. Sturm
James C. Sturm Princeton University
Sigurd Wagner
Sigurd Wagner Princeton University
Niraj K. Jha
Niraj K. Jha Princeton University
Michael C. McAlpine
Michael C. McAlpine University of Minnesota
Benton H. Calhoun
Benton H. Calhoun University of Virginia
Rajesh R. Naik
Rajesh R. Naik United States Air Force Research Laboratory
Fiorenzo G. Omenetto
Fiorenzo G. Omenetto Tufts University
Hu Tao
Hu Tao Chinese Academy of Sciences
Roman Genov
Roman Genov University of Toronto

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