World's Best Scientists 2026 revealed!

D-Index & Metrics

Electronics and Electrical Engineering

D-Index
46
Citations
8266
World Ranking
3394
National Ranking
59

Research.com Recognitions

  • 2016 - IEEE Fellow For contributions to energy-efficient VLSI circuits

Overview

Massimo Alioto is affiliated with the National University of Singapore in Singapore. Their research spans several fields within engineering, with a pronounced focus on electrical and electronic engineering. Alioto's work includes a significant contribution to biomedical engineering, hardware and architecture, computer vision and pattern recognition, and artificial intelligence.

The scientist's research topics cover a range of areas including analog and mixed-signal circuit design, physical unclonable functions (PUFs) and hardware security, advancements in semiconductor devices and circuit design, advanced memory and neural computing, low-power high-performance VLSI design, integrated circuits and semiconductor failure analysis, as well as semiconductor materials and devices.

Recent publications by Massimo Alioto include:

  • "Design of Digital OTAs With Operation Down to 0.3 V and nW Power for Direct Harvesting" (2021) in IEEE Transactions on Circuits and Systems I Regular Papers
  • "In-Memory Unified TRNG and Multi-Bit PUF for Ubiquitous Hardware Security" (2021) in IEEE Journal of Solid-State Circuits
  • "Fully Digital Rail-to-Rail OTA With Sub-1000-μm² Area, 250-mV Minimum Supply, and nW Power at 150-pF Load in 180 nm" (2020) in IEEE Solid-State Circuits Letters
  • "Fully Synthesizable Low-Area Analogue-to-Digital Converters With Minimal Design Effort Based on the Dyadic Digital Pulse Modulation" (2020) in IEEE Access
  • "Trimming-Less Voltage Reference for Highly Uncertain Harvesting Down to 0.25 V, 5.4 pW" (2021) in IEEE Journal of Solid-State Circuits

Frequent co-authors collaborating with Alioto include:

  • Amara Amara
  • Manuel Delgado-Restituto
  • Ricardo Reis
  • Nicole McFarlane
  • Alon Ascoli

Massimo Alioto's publications are frequently found in several IEEE venues, notably:

  • IEEE Transactions on Circuits and Systems I Regular Papers (48 publications)
  • IEEE Journal of Solid-State Circuits (15 publications)
  • IEEE Transactions on Circuits and Systems for Video Technology (11 publications)
  • IEEE Journal on Emerging and Selected Topics in Circuits and Systems (6 publications)
  • IEEE Solid-State Circuits Letters (5 publications)

Alioto was named an IEEE Fellow in 2016 for contributions to energy-efficient VLSI circuits.

Best Publications

  • Ultra-Low Power VLSI Circuit Design Demystified and Explained: A Tutorial

    M. Alioto

  • Analysis and comparison on full adder block in submicron technology

    M. Alioto;G. Palumbo

  • Understanding the Effect of Process Variations on the Delay of Static and Domino Logic

    Massimo Alioto;Gaetano Palumbo;Melita Pennisi

  • Understanding DC Behavior of Subthreshold CMOS Logic Through Closed-Form Analysis

    Massimo Alioto

  • Model and Design of Bipolar and MOS Current-Mode Logic: CML, ECL and SCL Digital Circuits

    Massimo Alioto;Gaetano Palumbo

  • Enabling the Internet of Things: From Integrated Circuits to Integrated Systems

    Massimo Alioto

  • Leakage Power Analysis Attacks: A Novel Class of Attacks to Nanometer Cryptographic Circuits

    M. Alioto;L. Giancane;G. Scotti;A. Trifiletti

  • Analysis and Comparison in the Energy-Delay-Area Domain of Nanometer CMOS Flip-Flops: Part I—Methodology and Design Strategies

    M Alioto;E Consoli;G Palumbo

  • Design strategies for source coupled logic gates

    M. Alioto;G. Palumbo

  • General Strategies to Design Nanometer Flip-Flops in the Energy-Delay Space

    Massimo Alioto;Elio Consoli;Gaetano Palumbo

  • Analysis and Comparison in the Energy-Delay-Area Domain of Nanometer CMOS Flip-Flops: Part II—Results and Figures of Merit

    M Alioto;E Consoli;G Palumbo

  • Conditional push-pull pulsed latches with 726fJ·ps energy-delay product in 65nm CMOS

    Elio Consoli;Massimo Alioto;Gaetano Palumbo;Jan Rabaey

  • Leakage–Delay Tradeoff in FinFET Logic Circuits: A Comparative Analysis With Bulk Technology

    M. Agostinelli;M. Alioto;D. Esseni;L. Selmi

  • Variations in Nanometer CMOS Flip-Flops: Part I—Impact of Process Variations on Timing

    Massimo Alioto;Elio Consoli;Gaetano Palumbo

  • 14.3 15fJ/b static physically unclonable functions for secure chip identification with <2% native bit instability and 140× Inter/Intra PUF hamming distance separation in 65nm

    Anastacia Alvarez;Wenfeng Zhao;Massimo Alioto

  • A feedback strategy to improve the entropy of a chaos-based random bit generator

    T. Addabbo;M. Alioto;A. Fort;S. Rocchi

  • Mixed Full Adder topologies for high-performance low-power arithmetic circuits

    M. Alioto;G. Di Cataldo;G. Palumbo

  • A Class of Maximum-Period Nonlinear Congruential Generators Derived From the Rényi Chaotic Map

    T. Addabbo;M. Alioto;A. Fort;A. Pasini

  • Trends in Hardware Security: From basics to ASICs

    Massimo Alioto

  • Impact of Supply Voltage Variations on Full Adder Delay: Analysis and Comparison

    M. Alioto;G. Palumbo

  • Flip-Flop Energy/Performance Versus Clock Slope and Impact on the Clock Network Design

    Massimo Alioto;Elio Consoli;Gaetano Palumbo

  • Fully Synthesizable PUF Featuring Hysteresis and Temperature Compensation for 3.2% Native BER and 1.02 fJ/b in 40 nm

    Sachin Taneja;Anastacia B. Alvarez;Massimo Alioto

Frequent Co-Authors

Gaetano Palumbo
Gaetano Palumbo University of Catania
Ada Fort
Ada Fort University of Siena
David Blaauw
David Blaauw University of Michigan–Ann Arbor
Dennis Sylvester
Dennis Sylvester University of Michigan–Ann Arbor
Felice Crupi
Felice Crupi University of Calabria
David Esseni
David Esseni University of Udine
Yusuf Leblebici
Yusuf Leblebici École Polytechnique Fédérale de Lausanne

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