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Gaetano Palumbo

Gaetano Palumbo

D-Index & Metrics

Electronics and Electrical Engineering

D-Index
58
Citations
10853
World Ranking
1900
National Ranking
39

Research.com Recognitions

  • 2007 - IEEE Fellow For contributions to analysis and design of high performance analog and digital circuits

Overview

Gaetano Palumbo is affiliated with the University of Catania in Italy. Their primary field of research is Engineering, with a significant focus on Electrical and Electronic Engineering. Other subfields include Biomedical Engineering, Mechanical Engineering, Automotive Engineering, and Cellular and Molecular Neuroscience.

Their work encompasses several main topics within engineering and circuit design:

  • Analog and Mixed-Signal Circuit Design
  • Innovative Energy Harvesting Technologies
  • Advancements in Semiconductor Devices and Circuit Design
  • Low-power high-performance VLSI design
  • Radio Frequency Integrated Circuit Design
  • Energy Harvesting in Wireless Networks
  • Wireless Power Transfer Systems

Gaetano Palumbo's recent published papers include:

  • "A Subthreshold Cross-Coupled Hybrid Charge Pump for 50-mV Cold-Start" (2020), IEEE Access
  • "Charge Pumps for Ultra-Low-Power Applications: Analysis, Design, and New Solutions" (2021), IEEE Transactions on Circuits & Systems II Express Briefs
  • "Charge Pump Improvement for Energy Harvesting Applications by Node Pre-Charging" (2020), IEEE Transactions on Circuits & Systems II Express Briefs
  • "Regulated Charge Pumps: A Comparative Study by Means of Verilog-AMS" (2020), Electronics
  • "Linear distribution of capacitance in Dickson charge pumps to reduce rise time" (2020), International Journal of Circuit Theory and Applications

Publication venues where Palumbo has frequently contributed include:

  • IEEE Access
  • Electronics
  • IEEE Transactions on Circuits and Systems I Regular Papers
  • IEEE Transactions on Circuits & Systems II Express Briefs
  • International Journal of Circuit Theory and Applications

The scientist collaborates regularly with several researchers. Frequent co-authors include:

  • Alfio Dario Grasso
  • Andrea Ballo
  • Giuseppe Scotti
  • Gianluca Giustolisi
  • Francesco Centurelli

Gaetano Palumbo was awarded the IEEE Fellow distinction in 2007 for contributions to analysis and design of high performance analog and digital circuits.

Best Publications

  • A low-voltage low-power voltage reference based on subthreshold MOSFETs

    G. Giustolisi;G. Palumbo;M. Criscione;F. Cutri

  • Charge Pump Circuits: An Overview on Design Strategies and Topologies

    G. Palumbo;D. Pappalardo

  • Analysis and comparison on full adder block in submicron technology

    M. Alioto;G. Palumbo

  • Charge-pump circuits: power-consumption optimization

    G. Palumbo;D. Pappalardo;M. Gaibotti

  • Understanding the Effect of Process Variations on the Delay of Static and Domino Logic

    Massimo Alioto;Gaetano Palumbo;Melita Pennisi

  • Model and Design of Bipolar and MOS Current-Mode Logic: CML, ECL and SCL Digital Circuits

    Massimo Alioto;Gaetano Palumbo

  • Advances in Reversed Nested Miller Compensation

    A.D. Grasso;G. Palumbo;S. Pennisi

  • Feedback Amplifiers: Theory and Design

    Gaetano Palumbo;Salvatore Pennisi

  • Design methodology and advances in nested-Miller compensation

    G. Palumbo;S. Pennisi

  • Design procedure for two-stage CMOS transconductance operational amplifiers: a tutorial

    G. Palmisano;G. Palumbo;S. Pennisi

  • A compensation strategy for two-stage CMOS opamps based on current buffer

    G. Palmisano;G. Palumbo

  • CMOS current amplifiers

    Giuseppe Palmisano;Gaetano Palumbo;Salvatore Pennisi

  • Design guidelines for reversed nested Miller compensation in three-stage amplifiers.

    Rosario Mita;Gaetano Palumbo;Salvatore Pennisi

  • Analysis and Comparison in the Energy-Delay-Area Domain of Nanometer CMOS Flip-Flops: Part I—Methodology and Design Strategies

    M Alioto;E Consoli;G Palumbo

  • Design strategies for source coupled logic gates

    M. Alioto;G. Palumbo

  • General Strategies to Design Nanometer Flip-Flops in the Energy-Delay Space

    Massimo Alioto;Elio Consoli;Gaetano Palumbo

  • Analysis and Comparison in the Energy-Delay-Area Domain of Nanometer CMOS Flip-Flops: Part II—Results and Figures of Merit

    M Alioto;E Consoli;G Palumbo

  • Conditional push-pull pulsed latches with 726fJ·ps energy-delay product in 65nm CMOS

    Elio Consoli;Massimo Alioto;Gaetano Palumbo;Jan Rabaey

  • Design Procedures for Three-Stage CMOS OTAs With Nested-Miller Compensation

    S.O. Cannizzaro;A.D. Grasso;R. Mita;G. Palumbo

  • Autonomous Energy-Efficient Wireless Sensor Network Platform for Home/Office Automation

    Crispino S. Abella;Salvo Bonina;Antonino Cucuccio;Salvatore D'Angelo

  • IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS Editor-in-Chief

    Gianluca Setti;Pamela Abshire;Bertan Bakkaloglu

Frequent Co-Authors

Salvatore Pennisi
Salvatore Pennisi University of Catania
Massimo Alioto
Massimo Alioto National University of Singapore
Giuseppe Palmisano
Giuseppe Palmisano University of Catania
Antonio J. Lopez-Martin
Antonio J. Lopez-Martin Universidad Publica De Navarra
Jan M. Rabaey
Jan M. Rabaey University of California, Berkeley
Ramon G. Carvajal
Ramon G. Carvajal University of Seville
Willy Sansen
Willy Sansen KU Leuven
Vojin G. Oklobdzija
Vojin G. Oklobdzija University of California, Davis
Mario di Bernardo
Mario di Bernardo University of Naples Federico II
Borivoje Nikolic
Borivoje Nikolic University of California, Berkeley

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