World's Best Scientists 2026 revealed!

D-Index & Metrics

Electronics and Electrical Engineering

D-Index
45
Citations
7566
World Ranking
3578
National Ranking
1312

Research.com Recognitions

  • 1996 - IEEE Fellow For contributions to computer architecture.

Overview

Vojin G. Oklobdzija is affiliated with the University of California, Davis in the United States. They have been recognized as an IEEE Fellow in 1996 for contributions to computer architecture.

No recent papers, frequent co-authors, publication venues, book publications, main fields of study, subfields of study, or main topics of work are listed in the available data.

Best Publications

  • Comparative analysis of master-slave latches and flip-flops for high-performance and low-power systems

    V. Stojanovic;V.G. Oklobdzija

  • Improved sense-amplifier-based flip-flop: design and measurements

    B. Nikolic;V.G. Oklobdzija;V. Stojanovic;Wenyan Jia

  • A method for speed optimized partial product reduction and generation of fast parallel multipliers using an algorithmic approach

    V.G. Oklobdzija;D. Villeger;S.S. Liu

  • Pass-transistor adiabatic logic using single power-clock supply

    V.G. Oklobdzija;D. Maksimovic;Fengcheng Lin

  • An algorithmic and novel design of a leading zero detector circuit: comparison with logic synthesis

    V.G. Oklobdzija

  • Clocked CMOS adiabatic logic with integrated single-phase power-clock supply

    D. Maksimovic;V.G. Oklobdzija;B. Nikolic;K.W. Current

  • Digital System Clocking: High-Performance and Low-Power Aspects

    Vojin G. Oklobdzija;Vladimir M. Stojanovic;Dejan M. Markovic;Nikola M. Nedovic

  • Optimal circuits for parallel multipliers

    P.F. Stelling;C.U. Martel;V.G. Oklobdzija;R. Ravi

  • Improving multiplier design by using improved column compression tree and optimized final adder in CMOS technology

    V.G. Oklobdzija;D. Villeger

  • Instruction control mechanism for a computing system with register renaming, map table and queues indicating available registers

    John Cocke;Gregory F. Grohoski;Vojin G. Oklobdzija

  • Comparison of high-performance VLSI adders in the energy-delay space

    V.G. Oklobdzija;B.R. Zeydel;H.Q. Dao;S. Mathew

  • Integrated power clock generators for low energy logic

    D. Maksimovic;V.G. Oklobdzija

  • Conditional pre-charge techniques for power-efficient dual-edge clocking

    Nikola Nedovic;Marko Aleksic;Vojin G. Oklobdzija

  • Clocking and clocked storage elements in a multi-gigahertz environment

    V. G. Oklobdzija

  • Dual-edge triggered storage elements and clocking strategy for low-power systems

    N. Nedovic;V.G. Oklobdzija

  • A 110 GOPS/W 16-bit multiplier and reconfigurable PLA loop in 90-nm CMOS

    S.K. Hsu;S.K. Mathew;M.A. Anders;B.R. Zeydel

  • Energy-delay estimation technique for high-performance microprocessor VLSI adders

    V.G. Oklobdzija;B.R. Zeydel;H. Dao;S. Mathew

  • The Computer Engineering Handbook

    Vojin G. Oklobdzija

  • Sense amplifier-based flip-flop

    B. Nikolic;V. Stojanovic;V.G. Oklobdzija;Wenyan Jia

  • Conditional pre-charge techniques for power-efficient dual-edge clocking

    Unknown

  • Some optimal schemes for ALU implementation in VLSI technology

    Vojin G. Oklobdzija;Earl R. Barnes

  • IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS Editor-in-Chief

    Gianluca Setti;Pamela Abshire;Bertan Bakkaloglu

Frequent Co-Authors

Borivoje Nikolic
Borivoje Nikolic University of California, Berkeley
Vladimir Stojanovic
Vladimir Stojanovic University of California, Berkeley
Ram Krishnamurthy
Ram Krishnamurthy Intel (United States)
Dejan Markovic
Dejan Markovic University of California, Los Angeles
Dragan Maksimovic
Dragan Maksimovic University of Colorado Boulder
Sanu Mathew
Sanu Mathew Intel (United States)
Ali Keshavarzi
Ali Keshavarzi Stanford University
Niraj K. Jha
Niraj K. Jha Princeton University
Mark A. Anders
Mark A. Anders Intel (United States)
Antonio J. Lopez-Martin
Antonio J. Lopez-Martin Universidad Publica De Navarra

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