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Electronics and Electrical Engineering

D-Index
49
Citations
6334
World Ranking
3001
National Ranking
1126

Research.com Recognitions

  • 2020 - IEEE Fellow For contributions to the design of mixed-signal integrated circuits

Overview

Pavan Kumar Hanumolu is affiliated with the University of Illinois at Urbana-Champaign in the United States. Their research is primarily situated within the field of Engineering, with a focus on Electrical and Electronic Engineering, Biomedical Engineering, Computer Networks and Communications, and Hardware and Architecture.

Their main research topics include:

  • Advancements in PLL and VCO Technologies
  • Analog and Mixed-Signal Circuit Design
  • Photonic and Optical Devices
  • Advanced DC-DC Converters
  • Silicon Carbide Semiconductor Technologies
  • Optical Network Technologies
  • Radio Frequency Integrated Circuit Design

Pavan Kumar Hanumolu has published frequently in the IEEE Journal of Solid-State Circuits, contributing to key developments in their fields of study.

Selected recent papers include:

  • Hybrid Dickson Switched-Capacitor Converter With Wide Conversion Ratio in 65-nm CMOS, 2020, IEEE Journal of Solid-State Circuits
  • A 32-MHz, 34-μW Temperature-Compensated RC Oscillator Using Pulse Density Modulated Resistors, 2021, IEEE Journal of Solid-State Circuits
  • A 91.15% Efficient 2.3-5-V Input 10-35-V Output Hybrid Boost Converter for LED-Driver Applications, 2021, IEEE Journal of Solid-State Circuits
  • A 12-Gb/s 10-ns Turn-On Time Rapid ON/OFF Baud-Rate DFE Receiver in 65-nm CMOS, 2020, IEEE Journal of Solid-State Circuits
  • A 16-Gb/s -11.6-dBm OMA Sensitivity 0.7-pJ/bit Optical Receiver in 65-nm CMOS Enabled by Duobinary Sampling, 2021, IEEE Journal of Solid-State Circuits

Frequent co-authors include:

  • Mostafa G. Ahmed
  • Ahmed Elkholy
  • Robert C. N. Pilawa-Podgurski
  • Amr Khashaba
  • Junheng Zhu

In 2020, Pavan Kumar Hanumolu was named an IEEE Fellow, recognized for contributions to the design of mixed-signal integrated circuits.

Best Publications

  • Analysis of charge-pump phase-locked loops

    P.K. Hanumolu;M. Brownlee;K. Mayaram;Un-Ku Moon

  • A Design Procedure for All-Digital Phase-Locked Loops Based on a Charge-Pump Phase-Locked-Loop Analogy

    V. Kratyuk;P.K. Hanumolu;Un-Ku Moon;K. Mayaram

  • A 16mW 78dB-SNDR 10MHz-BW CT-ΔΣ ADC using residue-cancelling VCO-based quantizer

    Karthikeyan Reddy;Sachin Rao;Rajesh Inti;Brian Young

  • A Digital PLL With a Stochastic Time-to-Digital Converter

    V. Kratyuk;P.K. Hanumolu;K. Ok;Un-Ku Moon

  • A 3.7 mW Low-Noise Wide-Bandwidth 4.5 GHz Digital Fractional-N PLL Using Time Amplifier-Based TDC

    Ahmed Elkholy;Tejasvi Anand;Woo-Seok Choi;Amr Elshazly

  • Method for a Constant Loop Bandwidth in LC-VCO PLL Frequency Synthesizers

    Ting Wu;P.K. Hanumolu;K. Mayaram;Un-Ku Moon

  • Clock Multiplication Techniques Using Digital Multiplying Delay-Locked Loops

    A. Elshazly;R. Inti;B. Young;P. K. Hanumolu

  • A Wide-Tracking Range Clock and Data Recovery Circuit

    P.K. Hanumolu;Gu-Yeon Wei;Un-Ku Moon

  • A 16-mW 78-dB SNDR 10-MHz BW CT $\Delta \Sigma$ ADC Using Residue-Cancelling VCO-Based Quantizer

    K. Reddy;S. Rao;R. Inti;B. Young

  • A VCO Based Highly Digital Temperature Sensor With 0.034 °C/mV Supply Sensitivity

    Tejasvi Anand;Kofi A. A. Makinwa;Pavan Kumar Hanumolu

  • A Deterministic Digital Background Calibration Technique for VCO-Based ADCs

    Sachin Rao;Karthikeyan Reddy;Brian Young;Pavan Kumar Hanumolu

  • Low-Power Supply-Regulation Techniques for Ring Oscillators in Phase-Locked Loops Using a Split-Tuned Architecture

    A. Arakali;S. Gondi;P.K. Hanumolu

  • A 71dB SFDR open loop VCO-based ADC using 2-level PWM modulation

    Sachin Rao;Brian Young;Amr Elshazly;Wenjing Yin

  • A 0.5-to-2.5 Gb/s Reference-Less Half-Rate Digital CDR With Unlimited Frequency Acquisition Range and Improved Input Duty-Cycle Error Tolerance

    Rajesh Inti;Wenjing Yin;Amr Elshazly;Naga Sasidhar

  • A Noise-Shaping Time-to-Digital Converter Using Switched-Ring Oscillators—Analysis, Design, and Measurement Techniques

    Amr Elshazly;Sachin Rao;Brian Young;Pavan Kumar Hanumolu

  • A 0.9 V 92 dB Double-Sampled Switched-RC Delta-Sigma Audio ADC

    Min Gyu Kim;Gil-Cho Ahn;P.K. Hanumolu;Sang-Hyeon Lee

  • Analog Filter Design Using Ring Oscillator Integrators

    B. Drost;M. Talegaonkar;P. K. Hanumolu

  • A 0.5-GHz to 2.5-GHz PLL With Fully Differential Supply Regulated Tuning

    M. Brownlee;P.K. Hanumolu;K. Mayaram;Un-Ku Moon

  • A 0.7-to-3.5 GHz 0.6-to-2.8 mW Highly Digital Phase-Locked Loop With Bandwidth Tracking

    Wenjing Yin;R. Inti;A. Elshazly;B. Young

  • A 4-to-10.5 Gb/s Continuous-Rate Digital Clock and Data Recovery With Automatic Frequency Acquisition

    Guanghua Shu;Woo-Seok Choi;Saurabh Saxena;Mrunmay Talegaonkar

  • Frequency detector for fast frequency lock of digital PLLs

    V. Kratyuk;P.K. Hanumolu;U.-k. Moon;K. Mayaram

Frequent Co-Authors

Un-Ku Moon
Un-Ku Moon Oregon State University
K. Mayaram
K. Mayaram Oregon State University
Gabor C. Temes
Gabor C. Temes Oregon State University
Gu-Yeon Wei
Gu-Yeon Wei Harvard University
Robert C. N. Pilawa-Podgurski
Robert C. N. Pilawa-Podgurski University of California, Berkeley
Terri S. Fiez
Terri S. Fiez University of Colorado Boulder
Ramesh Harjani
Ramesh Harjani University of Minnesota
Kofi A. A. Makinwa
Kofi A. A. Makinwa Delft University of Technology
Bryan K. Casper
Bryan K. Casper Intel (United States)
Luca Benini
Luca Benini ETH Zurich

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