World's Best Scientists 2026 revealed!

D-Index & Metrics

Electronics and Electrical Engineering

D-Index
51
Citations
9159
World Ranking
2698
National Ranking
1022

Research.com Recognitions

  • 2009 - IEEE Fellow For contributions to low voltage complementary metal-oxide semiconductor mixed-signal technology

Overview

Un-Ku Moon is affiliated with Oregon State University in the United States. Their research focuses primarily on engineering, with an emphasis on electrical and electronic engineering, biomedical engineering, and atomic and molecular physics and optics.

The scientist's work covers several main topics including:

  • Analog and Mixed-Signal Circuit Design
  • Low-power high-performance VLSI design
  • Advancements in Semiconductor Devices and Circuit Design
  • Advancements in PLL and VCO Technologies
  • CCD and CMOS Imaging Sensors
  • Radio Frequency Integrated Circuit Design
  • Mechanical and Optical Resonators

Un-Ku Moon has contributed to notable publications in the following venues:

  • IEEE Journal of Solid-State Circuits
  • IEEE Transactions on Circuits and Systems I Regular Papers
  • 2022 IEEE International Symposium on Circuits and Systems (ISCAS)
  • 2022 IEEE International Solid-State Circuits Conference (ISSCC)
  • IEEE Transactions on Circuits & Systems II Express Briefs

Frequent coauthors include Gábor C. Temes, Hang Hu, Calvin Yoji Lee, Praveen Kumar Venkatachala, and Ahmed ElShater.

Recent papers by Un-Ku Moon include:

  • "A 77-dB-DR 0.65-mW 20-MHz 5th-Order Coupled Source Followers Based Low-Pass Filter" (2020), IEEE Journal of Solid-State Circuits
  • "A 0.0375mm2 203.5µW 108.8dB DR DT Single-Loop DSM Audio ADC Using a Single-Ended Ring-Amplifier-Based Integrator in 180nm CMOS" (2022), 2022 IEEE International Solid-State Circuits Conference (ISSCC)
  • "Noise-Shaping SAR ADC Using a Two-Capacitor Digitally Calibrated DAC With 82.6-dB SNDR and 90.9-dB SFDR" (2021), IEEE Transactions on Circuits and Systems I Regular Papers
  • "A Rail-to-Rail 12 MS/s 91.3 dB SNDR 94.1 dB DR Two-Step SAR ADC With Integrated Input Buffer Using Predictive Level-Shifting" (2023), IEEE Journal of Solid-State Circuits
  • "A Pseudo-Pseudo-Differential ADC Achieving 105dB SNDR in 10kHz Bandwidth Using Ring Amplifier Based Integrators" (2021), IEEE Transactions on Circuits & Systems II Express Briefs

Un-Ku Moon was recognized as an IEEE Fellow in 2009 for contributions to low voltage complementary metal-oxide semiconductor mixed-signal technology.

Best Publications

  • Wideband low-distortion delta-sigma ADC topology

    J. Silva;U. Moon;J. Steensgaard;G.C. Temes

  • Merged capacitor switching based SAR ADC with highest switching energy-efficiency

    V. Hariprasath;J. Guerber;S.-H. Lee;U.-K. Moon

  • Background calibration techniques for multistage pipelined ADCs with digital redundancy.

    Jipeng Li;Un-Ku Moon

  • Background digital calibration techniques for pipelined ADCs

    Un-Ku Moon;Bang-Sup Song

  • Ring amplifiers for switched-capacitor circuits

    Benjamin Hershberg;Skyler Weaver;Kazuki Sobue;Seiji Takeuchi

  • A CMOS self-calibrating frequency synthesizer

    W.B. Wilson;Un-Ku Moon;K.R. Lakshmikumar;Liang Dai

  • Integrated circuit having phase locked loop

    Un-Ku Moon;William B Wilson;ビー.ウィルソン ウィリアム;ムーン ウン−クー

  • Digitally Synthesized Stochastic Flash ADC Using Only Standard Digital Cells

    Skyler Weaver;Benjamin Hershberg;Un-Ku Moon

  • Analysis of charge-pump phase-locked loops

    P.K. Hanumolu;M. Brownlee;K. Mayaram;Un-Ku Moon

  • An Over-60 dB True Rail-to-Rail Performance Using Correlated Level Shifting and an Opamp With Only 30 dB Loop Gain

    B.R. Gregoire;Un-Ku Moon

  • A Design Procedure for All-Digital Phase-Locked Loops Based on a Charge-Pump Phase-Locked-Loop Analogy

    V. Kratyuk;P.K. Hanumolu;Un-Ku Moon;K. Mayaram

  • Adaptive digital correction of analog errors in MASH ADCs. II. Correction using test-signal injection

    P. Kiss;J. Silva;A. Wiesbauer;Tao Sun

  • A 0.6-V 82-dB delta-sigma audio ADC using switched-RC integrators

    Gil-Cho Ahn;Dong-Young Chang;Matthew E. Brown;Naoto Ozaki

  • A Digital PLL With a Stochastic Time-to-Digital Converter

    V. Kratyuk;P.K. Hanumolu;K. Ok;Un-Ku Moon

  • A 1.8-V 67-mW 10-bit 100-MS/s pipelined ADC using time-shifted CDS technique

    Jipeng Li;Un-Ku Moon

  • Method for a Constant Loop Bandwidth in LC-VCO PLL Frequency Synthesizers

    Ting Wu;P.K. Hanumolu;K. Mayaram;Un-Ku Moon

  • A Wide-Tracking Range Clock and Data Recovery Circuit

    P.K. Hanumolu;Gu-Yeon Wei;Un-Ku Moon

  • Stochastic Flash Analog-to-Digital Conversion

    S Weaver;B Hershberg;P Kurahashi;D Knierim

  • Design of a low-distortion 22-kHz fifth-order Bessel filter

    Un-Ku Moon;Bang-Sup Song

  • A 1-V 10-MHz clock-rate 13-bit CMOS /spl Delta//spl Sigma/ modulator using unity-gain-reset op amps

    M. Keskin;Un-Ku Moon;G.C. Temes

  • Comments on 'Split ADC' architecture for deterministic digital background calibration of a 16-bit 1-MS/s ADC"

    Jipeng Li;Un-Ku Moon;J.A. McNeill;M. Coln

Frequent Co-Authors

Gabor C. Temes
Gabor C. Temes Oregon State University
Pavan Kumar Hanumolu
Pavan Kumar Hanumolu University of Illinois at Urbana-Champaign
K. Mayaram
K. Mayaram Oregon State University
Gu-Yeon Wei
Gu-Yeon Wei Harvard University
Bryan K. Casper
Bryan K. Casper Intel (United States)
Terri S. Fiez
Terri S. Fiez University of Colorado Boulder
Franco Maloberti
Franco Maloberti University of Pavia
Behzad Razavi
Behzad Razavi University of California, Los Angeles
Peter R. Kinget
Peter R. Kinget Columbia University
Jan Mulder
Jan Mulder Broadcom (United States)

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