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Deog-Kyoon Jeong

Deog-Kyoon Jeong

D-Index & Metrics

Electronics and Electrical Engineering

D-Index
51
Citations
10012
World Ranking
2675
National Ranking
76

Overview

Deog-Kyoon Jeong is affiliated with Seoul National University in South Korea. Their research primarily focuses on the field of Engineering, with a significant emphasis on Electrical and Electronic Engineering. Additional subfields of their work include Biomedical Engineering, Hardware and Architecture, Nuclear and High Energy Physics, and Control and Systems Engineering.

The main topics addressed in Jeong's research encompass:

  • Advancements in PLL and VCO Technologies
  • Radio Frequency Integrated Circuit Design
  • Analog and Mixed-Signal Circuit Design
  • Semiconductor Lasers and Optical Devices
  • Photonic and Optical Devices
  • VLSI and Analog Circuit Testing
  • Advancements in Semiconductor Devices and Circuit Design

Jeong has contributed extensively to scientific literature across several frequent publication venues, including:

  • IEEE Transactions on Circuits & Systems II Express Briefs
  • IEEE Journal of Solid-State Circuits
  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems
  • 2022 37th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC)
  • JSTS Journal of Semiconductor Technology and Science

Significant recent papers authored or coauthored by Jeong are:

  • "A 0.1-pJ/b/dB 1.62-to-10.8-Gb/s Video Interface Receiver With Jointly Adaptive CTLE and DFE Using Biased Data-Level Reference," 2020, IEEE Journal of Solid-State Circuits
  • "A 4-20-Gb/s 1.87-pJ/b Continuous-Rate Digital CDR Circuit With Unlimited Frequency Acquisition Capability in 65-nm CMOS," 2020, IEEE Journal of Solid-State Circuits
  • "A Fast Droop-Recovery Event-Driven Digital LDO With Adaptive Linear/Binary Two-Step Search for Voltage Regulation in Advanced Memory," 2021, IEEE Transactions on Power Electronics
  • "Design Techniques for a 6.4-32-Gb/s 0.96-pJ/b Continuous-Rate CDR With Stochastic Frequency-Phase Detector," 2021, IEEE Journal of Solid-State Circuits
  • "An Output-Capacitor-Free Synthesizable Digital LDO Using CMP-Triggered Oscillator and Droop Detector," 2022, IEEE Journal of Solid-State Circuits

Frequent coauthors of Deog-Kyoon Jeong include:

  • Woorham Bae
  • Kwanseo Park
  • Kwang-Ho Lee
  • Jonghyun Oh
  • Minkyo Shim

In addition to journal and conference publications, Jeong has contributed to book literature, including the publication titled "Analysis and Design of CMOS Clocking Circuits for Low Phase Noise" in 2020, published by the Institution of Engineering and Technology.

Best Publications

  • An efficient charge recovery logic circuit

    Yong Moon;Deog-Kyoon Jeong

  • Communications architecture for transmission of data between memory bank caches and ports

    Dongyun Lee;Yeshik Shin;David D. Lee;Deog-Kyoon Jeong

  • An all-analog multiphase delay-locked loop using a replica delay line for wide-range operation and low-jitter performance

    Yongsam Moon;Jongsang Choi;Kyeongho Lee;Deog-Kyoon Jeong

  • Design of PLL-based clock generation circuits

    D.K. Jeong;G. Borriello;D.A. Hodges;R.H. Katz

  • A 0.18-/spl mu/m CMOS 3.5-gb/s continuous-time adaptive cable equalizer using enhanced low-frequency gain control method

    Jong-Sang Choi;Moon-Sang Hwang;Deog-Kyoon Jeong

  • A 960-Mb/s/pin interface for skew-tolerant bus using low jitter PLL

    Sungjoon Kim;Kyeongho Lee;Yongsam Moon;Deog-Kyoon Jeong

  • A fully integrated CMOS frequency synthesizer with charge-averaging charge pump and dual-path loop filter for PCS- and cellular-CDMA wireless systems

    Yido Koo;Hyungki Huh;Yongsik Cho;Jeongwoo Lee

  • A CMOS Serial Link for Fully Duplexed Data Communication

    Kyeongho Lee;Sungjoon Kim;Gijung Ahn;Deog-Kyoon Jeong

  • Reduction of pump current mismatch in charge-pump PLL

    M.-S. Hwang;J. Kim;D.-K. Jeong

  • A^3: Accelerating Attention Mechanisms in Neural Networks with Approximation

    Tae Jun Ham;Sung Jun Jung;Seonghak Kim;Young H. Oh

  • Data recovery using data eye tracking

    Sang-hyun Lee;Deog-Kyoon Jeong

  • Full-CMOS 2-GHz WCDMA direct conversion transmitter and receiver

    Kang-Yoon Lee;Seung-Wook Lee;Yido Koo;Hyoung-Ki Huh

  • A low-jitter 5000ppm spread spectrum clock generator for multi-channel SATA transceiver in 0.18/spl mu/m CMOS

    Hyung-Rok Lee;Ook Kim;Gijung Ahn;Deog-Kyoon Jeong

  • A Practical Implementation of IEEE 1588-2008 Transparent Clock for Distributed Measurement and Control Systems

    Jiho Han;Deog-Kyoon Jeong

  • Multi-gigabit-rate clock and data recovery based on blind oversampling

    Jaeha Kim;Deog-Kyoon Jeong

  • A 5-Gb/s 0.25-/spl mu/m CMOS jitter-tolerant variable-interval oversampling clock/data recovery circuit

    Sang-Hyun Lee;Moon-Sang Hwang;Youngdon Choi;Sungioon Kim

  • A Single-Inductor, Multiple-Channel Current-Balancing LED Driver for Display Backlight Applications

    Hyun-Chang Kim;Chang Soo Yoon;Deog-Kyoon Jeong;Jaeha Kim

  • Single chip cmos transmitter/receiver and method of using same

    Kyeongho Lee;Deog-Kyoon Jeong;Joonbae Park;Wonchan Kim

  • A 20-GHz phase-locked loop for 40-gb/s serializing transmitter in 0.13-/spl mu/m CMOS

    Jaeha Kim;Jeong-Kyoum Kim;Bong-Joon Lee;Namhoon Kim

  • A 1.0–4.0-Gb/s All-Digital CDR With 1.0-ps Period Resolution DCO and Adaptive Proportional Gain Control

    Heesoo Song;Deok-Soo Kim;Do-Hwan Oh;Suhwan Kim

  • A CMOS Serial Link for Fully Duplexed Data Communication(Special Issue on the 1994 VLSI Circuits Symposium)

    Kyeongho Lee;Sungjoon Kim;Gijung Ahn;Deog-Kyoon Jeong

Frequent Co-Authors

Dong-il Dan Cho
Dong-il Dan Cho Seoul National University
Cheol Seong Hwang
Cheol Seong Hwang Seoul National University
Chulwoo Kim
Chulwoo Kim Korea University
Borivoje Nikolic
Borivoje Nikolic University of California, Berkeley

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