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Electronics and Electrical Engineering

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5546
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Overview

Salvatore Levantino is a researcher affiliated with the Polytechnic University of Milan in Italy, specializing in engineering with a strong focus on electrical and electronic engineering. Their academic output spans numerous topics within the broader field, reflecting a concentrated expertise in integrated circuit and systems design.

Their research contributions are mainly focused on advancements in phase-locked loop (PLL) and voltage-controlled oscillator (VCO) technologies, covering:

  • Advancements in PLL and VCO Technologies
  • Radio Frequency Integrated Circuit Design
  • Semiconductor Lasers and Optical Devices
  • Analog and Mixed-Signal Circuit Design
  • Advanced DC-DC Converters
  • Photonic and Optical Devices
  • Electromagnetic Compatibility and Noise Suppression

The researcher has also contributed to subfields such as biomedical engineering, automotive engineering, aerospace engineering, and control and systems engineering.

Salvatore Levantino has frequently published in various IEEE venues, including:

  • IEEE Journal of Solid-State Circuits
  • IEEE Transactions on Power Electronics
  • IEEE Transactions on Circuits and Systems I Regular Papers
  • 2022 IEEE Custom Integrated Circuits Conference (CICC)
  • IEEE Solid-State Circuits Letters

Among the most recent papers authored or coauthored by Levantino are:

  • A 66-fs-rms Jitter 12.8-to-15.2-GHz Fractional-N Bang-Bang PLL With Digital Frequency-Error Recovery for Fast Locking (2020, IEEE Journal of Solid-State Circuits)
  • A 12.5-GHz Fractional-N Type-I Sampling PLL Achieving 58-fs Integrated Jitter (2021, IEEE Journal of Solid-State Circuits)
  • A Comprehensive Phase Noise Analysis of Bang-Bang Digital PLLs (2021, IEEE Transactions on Circuits and Systems I Regular Papers)
  • A Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching Achieving 68.6 fs-rms-Total-Integrated-Jitter and 1.56 μs-Locking-Time (2022, IEEE Journal of Solid-State Circuits)
  • A 12.9-to-15.1-GHz Digital PLL Based on a Bang-Bang Phase Detector With Adaptively Optimized Noise Shaping (2021, IEEE Journal of Solid-State Circuits)

Collaborations have been an important part of Levantino's academic activity, with frequent coauthors including Carlo Samori, Andrea L. Lacaita, Luca Bertulessi, Francesco Tesolin, and Simone M. Dartizio.

Best Publications

  • Frequency dependence on bias current in 5 GHz CMOS VCOs: impact on tuning range and flicker noise upconversion

    S. Levantino;C. Samori;A. Bonfanti;S.L.J. Gierkink

  • A low-phase-noise 5-GHz CMOS quadrature VCO using superharmonic coupling

    S.L.J. Gierkink;S. Levantino;R.C. Frye;C. Samori

  • A 13.5-mW 5-GHz frequency synthesizer with dynamic-logic frequency divider

    S. Pellerano;S. Levantino;C. Samori;A.L. Lacaita

  • A 2.9–4.0-GHz Fractional-N Digital PLL With Bang-Bang Phase Detector and 560- ${ m fs}_{ m rms}$ Integrated Jitter at 4.5-mW Power

    Davide Tasca;Marco Zanuso;Giovanni Marzin;Salvatore Levantino

  • Phase noise in digital frequency dividers

    S. Levantino;L. Romano;S. Pellerano;C. Samori

  • An Adaptive Pre-Distortion Technique to Mitigate the DTC Nonlinearity in Digital PLLs

    Salvatore Levantino;Giovanni Marzin;Carlo Samori

  • Integrated Frequency Synthesizers for Wireless Systems

    Andrea Leonardo Lacaita;Salvatore Levantino;Carlo Samori

  • Noise Analysis and Minimization in Bang-Bang Digital PLLs

    M. Zanuso;D. Tasca;S. Levantino;A. Donadel

  • AM-to-PM conversion in varactor-tuned oscillators

    S. Levantino;C. Samori;A. Zanchi;A.L. Lacaita

  • A 20 Mb/s Phase Modulator Based on a 3.6 GHz Digital PLL With −36 dB EVM at 5 mW Power

    Giovanni Marzin;Salvatore Levantino;Carlo Samori;Andrea Lacaita

  • A Wideband 3.6 GHz Digital ΔΣ Fractional-N PLL With Phase Interpolation Divider and Digital Spur Cancellation

    M Zanuso;S Levantino;C Samori;A L Lacaita

  • Multiphase LC oscillators

    L. Romano;S. Levantino;C. Samori;A.L. Lacaita

  • A 2-V 2.5-GHz-104-dBc/Hz at 100 kHz fully integrated VCO with wide-band low-noise automatic amplitude control loop

    A. Zanchi;C. Samori;S. Levantino;A.L. Lacaita

  • Phase noise and accuracy in quadrature oscillators

    L. Romano;S. Levantino;A. Bonfanti;C. Samori

  • Suppression of Flicker Noise Up-Conversion in a 65-nm CMOS VCO in the 3.0-to-3.6 GHz Band

    Federico Pepe;Andrea Bonfanti;Salvatore Levantino;Carlo Samori

  • A -94 dBc/Hz@100 kHz, fully-integrated, 5-GHz, CMOS VCO with 18% tuning range for Bluetooth applications

    C. Samori;S. Levantino;V. Boccuzzi

  • 21.1 A 1.7GHz MDLL-based fractional-N frequency synthesizer with 1.4ps RMS integrated jitter and 3mW power using a 1b TDC

    Giovanni Marucci;Andrea Fenaroli;Giovanni Marzin;Salvatore Levantino

  • A 23-GHz Low-Phase-Noise Digital Bang–Bang PLL for Fast Triangular and Sawtooth Chirp Modulation

    Dmytro Cherniak;Luigi Grimaldi;Luca Bertulessi;Carlo Samori

  • Analysis and Design of Low-Jitter Digital Bang-Bang Phase-Locked Loops

    Giovanni Marucci;Salvatore Levantino;Paolo Maffezzoni;Carlo Samori

  • Time-to-Digital Converter for Frequency Synthesis Based on a Digital Bang-Bang DLL

    M. Zanuso;P. Madoglio;S. Levantino;C. Samori

  • PLL With Phase Interpolation Divider and Digital Spur Cancellation

    Marzo Zanuso;Salvatore Levantino;Carlo Samori;Andrea L. Lacaita

  • Integrated Frequency Synthesizers for Wireless Systems: Reactive components in oscillators

    Andrea Leonardo Lacaita;Salvatore Levantino;Carlo Samori

Frequent Co-Authors

Carlo Samori
Carlo Samori Polytechnic University of Milan
Andrea L. Lacaita
Andrea L. Lacaita Polytechnic University of Milan
Michael Peter Kennedy
Michael Peter Kennedy University College Dublin
Pietro Andreani
Pietro Andreani Lund University

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