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Jan Craninckx

Jan Craninckx

D-Index & Metrics

Electronics and Electrical Engineering

D-Index
58
Citations
11484
World Ranking
1890
National Ranking
44

Research.com Recognitions

  • 2014 - IEEE Fellow For contributions to the design of CMOS RF transceivers

Overview

Jan Craninckx is affiliated with Imec in Belgium and specializes in engineering with a focus on electrical and electronic engineering, biomedical engineering, atomic and molecular physics and optics, artificial intelligence, and aerospace engineering.

The primary research topics include:

  • Radio Frequency Integrated Circuit Design
  • Analog and Mixed-Signal Circuit Design
  • Advancements in Semiconductor Devices and Circuit Design
  • Advancements in PLL and VCO Technologies
  • CCD and CMOS Imaging Sensors
  • Quantum and Electron Transport Phenomena
  • Acoustic Wave Resonator Technologies

Frequent coauthors of Jan Craninckx are:

  • Piet Wambacq
  • Nereo Markulić
  • Ewout Martens
  • Pratap Tumkur Renukaswamy
  • Jorge Lagos

Publications have appeared mostly in the following venues:

  • IEEE Journal of Solid-State Circuits
  • IEEE Transactions on Circuits and Systems I Regular Papers
  • IEEE Transactions on Circuits & Systems II Express Briefs
  • IEEE Solid-State Circuits Letters
  • IEEE Solid-State Circuits Magazine

Some recent papers include:

  • A Wideband 62-mW 60-GHz FMCW Radar in 28-nm CMOS, 2021, IEEE Transactions on Microwave Theory and Techniques
  • A 10.1-ENOB, 6.2-fJ/conv.-step, 500-MS/s, Ringamp-Based Pipelined-SAR ADC With Background Calibration and Dynamic Reference Regulation in 16-nm CMOS, 2022, IEEE Journal of Solid-State Circuits
  • Analysis of a 28-nm CMOS Fast-Lock Bang-Bang Digital PLL With 220-fs RMS Jitter for Millimeter-Wave Communication, 2020, IEEE Journal of Solid-State Circuits
  • A D-Band Low-Power and High-Efficiency Frequency Multiply-by-9 FMCW Radar Transmitter in 28-nm CMOS, 2022, IEEE Journal of Solid-State Circuits
  • A 4-GS/s 10-ENOB 75-mW Ringamp ADC in 16-nm CMOS With Background Monitoring of Distortion, 2021, IEEE Journal of Solid-State Circuits

Jan Craninckx has also authored books published by Morgan & Claypool Publishers and River Publishers eBooks:

  • PLL Modulation and Mixed-Signal Calibration Techniques for FMCW Radar, 2024
  • Technologies Enabling Future Mobile Connectivity & Sensing, 2023

An award received includes the IEEE Fellow distinction in 2014 for contributions to the design of CMOS RF transceivers.

Best Publications

  • A 1.8-GHz low-phase-noise CMOS VCO using optimized hollow spiral inductors

    J. Craninckx;M.S.J. Steyaert

  • A fully integrated CMOS DCS-1800 frequency synthesizer

    J. Craninckx;M.S.J. Steyaert

  • A 65fJ/Conversion-Step 0-to-50MS/s 0-to-0.7mW 9b Charge-Sharing SAR ADC in 90nm Digital CMOS

    J. Craninckx;G. Van der Plas

  • A 1.75-GHz/3-V dual-modulus divide-by-128/129 prescaler in 0.7-/spl mu/m CMOS

    J. Craninckx;M.S.J. Steyaert

  • A 1.8-GHz CMOS low-phase-noise voltage-controlled oscillator with prescaler

    J. Craninckx;M.S.J. Steyaert

  • Analog/RF Solutions Enabling Compact Full-Duplex Radios

    B. Debaillie;J.D.A. van den Broek;C. Lavín;B. van Liempd

  • Low-noise voltage-controlled oscillators using enhanced LC-tanks

    J. Craninckx;M. Steyaert

  • Wireless CMOS Frequency Synthesizer Design

    J. Craninckx;M. Steyaert

  • An 820μW 9b 40MS/s Noise-Tolerant Dynamic-SAR ADC in 90nm Digital CMOS

    V. Giannini;P. Nuzzo;V. Chironi;A. Baschirotto

  • A 40 nm CMOS 0.4–6 GHz Receiver Resilient to Out-of-Band Blockers

    J. Borremans;G. Mandal;V. Giannini;B. Debaillie

  • Flexible Baseband Analog Circuits for Software-Defined Radio Front-Ends

    V. Giannini;J. Craninckx;S. D'Amico;A. Baschirotto

  • A 9.2–12.7 GHz Wideband Fractional-N Subsampling PLL in 28 nm CMOS With 280 fs RMS Jitter

    Kuba Raczkowski;Nereo Markulic;Benjamin Hershberg;Jan Craninckx

  • A 0.65-to-1.4 nJ/Burst 3-to-10 GHz UWB All-Digital TX in 90 nm CMOS for IEEE 802.15.4a

    J. Ryckaert;G. Van der Plas;V. De Heyn;C. Desset

  • A 2-mm $^{2}$ 0.1–5 GHz Software-Defined Radio Receiver in 45-nm Digital CMOS

    V. Giannini;P. Nuzzo;C. Soens;K. Vengattaramane

  • A fully integrated spiral-LC CMOS VCO set with prescaler for GSM and DCS-1800 systems

    J. Craninckx;M. Steyaert;H. Miyakawa

  • A fully-integrated single-chip SOC for Bluetooth

    F.O. Eynde;J.-J. Schmit;V. Charlier;R. Alexandre

  • Wideband VCO With Simultaneous Switching of Frequency Band, Active Core, and Varactor Size

    D. Hauspie;Eun-Chul Park;J. Craninckx

  • A Fully Reconfigurable Software-Defined Radio Transceiver in 0.13μm CMOS

    J. Craninckx;M. Liu;D. Hauspie;V. Giannini

  • A 1.7 mW 11b 250 MS/s 2-Times Interleaved Fully Dynamic Pipelined SAR ADC in 40 nm Digital CMOS

    Bob Verbruggen;Masao Iriguchi;Jan Craninckx

  • A 79-GHz 2 $ imes $ 2 MIMO PMCW Radar SoC in 28-nm CMOS

    Davide Guermandi;Qixian Shi;Andy Dewilde;Veerle Derudder

  • An analytical model of planar inductors on lowly doped silicon substrates for high frequency analog design up to 3 GHz

    J. Crols;P. Kinget;J. Craninckx;M. Steyaert

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