2014 - IEEE Fellow For contributions to the design of CMOS RF transceivers
Jan Craninckx is exploring Antenna (radio) as part of his Duplexer and RF front end and Antenna (radio) studies. By researching both Duplexer and Antenna (radio), he produces research that crosses academic boundaries. Many of his studies on RF front end apply to Radio frequency as well. In his papers, Jan Craninckx integrates diverse fields, such as Radio frequency and Software-defined radio. He frequently studies issues relating to Electronic engineering and Software-defined radio. As part of his studies on Electronic engineering, he often connects relevant subjects like Wideband. He undertakes multidisciplinary investigations into Wideband and Baseband in his work. Jan Craninckx brings together Electrical engineering and Acoustics to produce work in his papers. He performs multidisciplinary study on Acoustics and Electrical engineering in his works.
Other disciplines of study, such as Voltage-controlled oscillator and Phase-locked loop, are mixed together with his Phase noise studies. He integrates Voltage-controlled oscillator with Phase noise in his study. His study on Electrical engineering is mostly dedicated to connecting different topics, such as Wideband. Many of his studies involve connections with topics such as Electronic engineering and Wideband. His Electronic engineering study frequently draws connections to other fields, such as Transceiver. His study connects Optoelectronics and CMOS. The study of Optoelectronics is intertwined with the study of CMOS in a number of ways. He performs multidisciplinary study on Voltage and Capacitor in his works. In his research, Jan Craninckx undertakes multidisciplinary study on Capacitor and Voltage.
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A 1.8-GHz low-phase-noise CMOS VCO using optimized hollow spiral inductors
J. Craninckx;M.S.J. Steyaert.
IEEE Journal of Solid-state Circuits (1997)
A fully integrated CMOS DCS-1800 frequency synthesizer
J. Craninckx;M.S.J. Steyaert.
international solid-state circuits conference (1998)
A 65fJ/Conversion-Step 0-to-50MS/s 0-to-0.7mW 9b Charge-Sharing SAR ADC in 90nm Digital CMOS
J. Craninckx;G. Van der Plas.
international solid-state circuits conference (2007)
A 1.75-GHz/3-V dual-modulus divide-by-128/129 prescaler in 0.7-/spl mu/m CMOS
J. Craninckx;M.S.J. Steyaert.
IEEE Journal of Solid-state Circuits (1996)
A 1.8-GHz CMOS low-phase-noise voltage-controlled oscillator with prescaler
J. Craninckx;M.S.J. Steyaert.
IEEE Journal of Solid-state Circuits (1995)
Low-noise voltage-controlled oscillators using enhanced LC-tanks
J. Craninckx;M. Steyaert.
IEEE Transactions on Circuits and Systems Ii: Analog and Digital Signal Processing (1995)
Wireless CMOS Frequency Synthesizer Design
J. Craninckx;M. Steyaert.
(2013)
An 820μW 9b 40MS/s Noise-Tolerant Dynamic-SAR ADC in 90nm Digital CMOS
V. Giannini;P. Nuzzo;V. Chironi;A. Baschirotto.
international solid-state circuits conference (2008)
Analog/RF Solutions Enabling Compact Full-Duplex Radios
B. Debaillie;J.D.A. van den Broek;C. Lavín;B. van Liempd.
IEEE Journal on Selected Areas in Communications (2014)
A 40 nm CMOS 0.4–6 GHz Receiver Resilient to Out-of-Band Blockers
J. Borremans;G. Mandal;V. Giannini;B. Debaillie.
IEEE Journal of Solid-state Circuits (2011)
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