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Tadahiro Kuroda

Tadahiro Kuroda

D-Index & Metrics

Electronics and Electrical Engineering

D-Index
58
Citations
10729
World Ranking
1903
National Ranking
65

Overview

Tadahiro Kuroda is a researcher affiliated with the University of Tokyo in Japan. Their academic work primarily spans the fields of Engineering and Computer Science, with a focused emphasis on Electrical and Electronic Engineering, Media Technology, Hardware and Architecture, Artificial Intelligence, and Computer Networks and Communications.

The research contributions of Tadahiro Kuroda encompass several main topics, including:

  • 3D IC and TSV technologies
  • Semiconductor materials and devices
  • Advanced Memory and Neural Computing
  • Semiconductor Lasers and Optical Devices
  • RFID technology advancements
  • Interconnection Networks and Systems
  • Low-power high-performance VLSI design

Their recent scholarly papers include:

  • mmWave-YOLO: A mmWave Imaging Radar-Based Real-Time Multiclass Object Recognition System for ADAS Applications, 2022, IEEE Transactions on Instrumentation and Measurement
  • A 96-MB 3D-Stacked SRAM Using Inductive Coupling With 0.4-V Transmitter, Termination Scheme and 12:1 SerDes in 40-nm CMOS, 2020, IEEE Transactions on Circuits and Systems I Regular Papers
  • A 16 nJ/Classification FPGA-Based Wired-Logic DNN Accelerator Using Fixed-Weight Non-Linear Neural Net, 2021, IEEE Journal on Emerging and Selected Topics in Circuits and Systems
  • A 7-nm FinFET 1.2-TB/s/mm2 3D-Stacked SRAM Module With 0.7-pJ/b Inductive Coupling Interface Using Over-SRAM Coil and Manchester-Encoded Synchronous Transceiver, 2022, IEEE Journal of Solid-State Circuits
  • A 6-Gb/s Inductively-Powered Non-Contact Connector With Rotatable Transmission Line Coupler and Interface Bridge IC, 2021, IEEE Journal of Solid-State Circuits

Their frequent collaborators include Mototsugu Hamada, Atsutake Kosuge, K. Shiba, Mitsuji Okada, and Saito Shibata.

Tadahiro Kuroda has published extensively in venues such as:

  • Japanese Journal of Applied Physics
  • IEEE Solid-State Circuits Letters
  • IEEE Transactions on Circuits and Systems I Regular Papers
  • IEEE Journal of Solid-State Circuits
  • IEEE Transactions on Instrumentation and Measurement

In addition to journal articles, Kuroda has contributed to book publications including "Wireless Interface Technologies for 3D IC and Module Integration" (2021) published by Cambridge University Press and "The Super-Evolution of Semiconductors" (2024) published by Morgan & Claypool Publishers.

Best Publications

  • A 0.9-V, 150-MHz, 10-mW, 4 mm/sup 2/, 2-D discrete cosine transform core processor with variable threshold-voltage (VT) scheme

    T. Kuroda;T. Fujita;S. Mita;T. Nagamatsu

  • Variable supply-voltage scheme for low-power high-speed CMOS digital design

    T. Kuroda;K. Suzuki;S. Mita;T. Fujita

  • Split Capacitor DAC Mismatch Calibration in Successive Approximation ADC

    Yanfei Chen;Xiaolei Zhu;Hirotaka Tamura;Masaya Kibune

  • 1.27Gb/s/pin 3mW/pin wireless superconnect (WSC) interface scheme

    K. Kanda;D.D. Antono;K. Ishida;H. Kawaguchi

  • A 0.5 V 1.1 MS/sec 6.3 fJ/Conversion-Step SAR-ADC With Tri-Level Comparator in 40 nm CMOS

    A. Shikata;R. Sekimoto;T. Kuroda;H. Ishikuro

  • A 60 mW MPEG4 video codec using clustered voltage scaling with variable supply-voltage scheme

    M. Takahashi;M. Hamada;M. Hamada;T. Nishikawa;T. Nishikawa;H. Arakida

  • Analysis and design of inductive coupling and transceiver circuit for inductive inter-chip wireless superconnect

    Noriyuki Miura;Daisuke Mizoguchi;Takayasu Sakurai;Tadahiro Kuroda

  • A CMOS ultra-wideband impulse radio transceiver for 1-mb/s data communications and /spl plusmn/2.5-cm range finding

    T. Terada;S. Yoshizumi;M. Muqsith;Y. Sanada

  • A 1.2Gb/s/pin wireless superconnect based on inductive inter-chip signaling (IIS)

    D. Mizoguchi;Y.B. Yusof;N. Miura;T. Sakura

  • BRein Memory: A Single-Chip Binary/Ternary Reconfigurable in-Memory Deep Neural Network Accelerator Achieving 1.4 TOPS at 0.6 W

    Kota Ando;Kodai Ueyoshi;Kentaro Orimo;Haruyoshi Yonekawa

  • 50% active-power saving without speed degradation using standby power reduction (SPR) circuit

    K. Seta;H. Hara;T. Kuroda;M. Kakumu

  • A 0.14pJ/b Inductive-Coupling Inter-Chip Data Transceiver with Digitally-Controlled Precise Pulse Shaping

    N. Miura;H. Ishikuro;T. Sakurai;T. Kuroda

  • A 750 Mb/s, 12 pJ/b, 6-to-10 GHz CMOS IR-UWB Transmitter With Embedded On-Chip Antenna

    V.V. Kulkarni;M. Muqsith;K. Niitsu;H. Ishikuro

  • A 1Tb/s 3W inductive-coupling transceiver for inter-chip clock and data link

    N. Miura;D. Mizoguchi;M. Inoue;K. Niitsu

  • A CMOS ultra-wideband impulse radio transceiver for 1-Mb/s data communications and ±2.5-cm range finding

    Takahide Terada;Shingo Yoshizumi;Muhammad Muqsith;Yukitoshi Sanada

  • A 60 MHz 240 mW MPEG-4 video-phone LSI with 16 Mb embedded DRAM

    T. Nishikawa;M. Takahashi;M. Hamada;T. Takayanagi;T. Takayanagi

  • A scalable 3D heterogeneous multi-core processor with inductive-coupling thruchip interface

    Noriyuki Miura;Yusuke Koizumi;Eiichi Sasaki;Yasuhiro Take

  • A Scalable 3D Heterogeneous Multicore with an Inductive ThruChip Interface

    Noriyuki Miura;Yusuke Koizumi;Yasuhiro Take;Hiroki Matsutani

  • Low-power CMOS digital design with dual embedded adaptive power supplies

    T. Kuroda;M. Hamada

  • A bitline leakage compensation scheme for low-voltage SRAMs

    K. Agawa;H. Hara;T. Takayanagi;T. Kuroda

  • Using Clustered Voltage Scaling with Variable Supply-Voltage Scheme

    Masafumi Takahashi;Mototsugu Hamada;Tsuyoshi Nishikawa;Hideho Arakida

Frequent Co-Authors

Takayasu Sakurai
Takayasu Sakurai University of Tokyo
Tsuyoshi Sekitani
Tsuyoshi Sekitani Osaka University
Takeshi Yanagida
Takeshi Yanagida University of Tokyo
Radu Marculescu
Radu Marculescu The University of Texas at Austin
Makoto Takamiya
Makoto Takamiya University of Tokyo
Ken Takeuchi
Ken Takeuchi University of Tokyo

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