2023 - Research.com Computer Science in Taiwan Leader Award
2022 - Research.com Computer Science in Taiwan Leader Award
2016 - Fellow, National Academy of Inventors
2001 - IEEE Fellow For contributions to algorithm and architecture design for video coding systems.
His main research concerns Motion estimation, Artificial intelligence, Computer vision, Computer hardware and Real-time computing. His Motion estimation study incorporates themes from Data compression, Motion compensation, Memory bandwidth and Search algorithm. His work carried out in the field of Data compression brings together such families of science as Image processing and Transform coding.
In Computer vision, he works on issues like Interpolation, which are connected to Electronic engineering, Enhanced Data Rates for GSM Evolution, Quality, Depth filter and Motion. The Computer hardware study combines topics in areas such as Macroblock, JPEG 2000, Hardware architecture and Context-adaptive binary arithmetic coding. His study explores the link between Real-time computing and topics such as Chip that cross with problems in Minimax and Signal compression.
Liang-Gee Chen mostly deals with Artificial intelligence, Computer vision, Computer hardware, Motion estimation and Algorithm. His Artificial intelligence research includes themes of Computer graphics and Pattern recognition. His Computer hardware research incorporates themes from Data compression, Real-time computing, Embedded system and Hardware architecture.
He interconnects Transform coding, Image processing, Image compression, JPEG 2000 and Codec in the investigation of issues within Data compression. His work in Motion estimation addresses subjects such as Parallel computing, which are connected to disciplines such as Auxiliary memory. His Algorithm research incorporates elements of Discrete wavelet transform and Very-large-scale integration.
Artificial intelligence, Computer vision, Feature extraction, Computer hardware and Pattern recognition are his primary areas of study. The study incorporates disciplines such as Machine learning, Computer graphics and Perception in addition to Artificial intelligence. His Feature extraction study also includes fields such as
His study in Computer hardware is interdisciplinary in nature, drawing from both Algorithm design, Embedded system and Speedup. The concepts of his Embedded system study are interwoven with issues in Digital signal processing, Stream processing and Parallel processing. His Memory management study combines topics in areas such as Memory architecture and Parallel computing.
His primary areas of investigation include Artificial intelligence, Computer vision, Computer hardware, Depth map and Pixel. His Artificial intelligence course of study focuses on Speech recognition and Phonocardiogram. His Computer vision study frequently draws connections between adjacent fields such as Real-time computing.
His Computer hardware research is multidisciplinary, incorporating elements of Voltage spike, Algorithm design, Graphics processing unit, Embedded system and Context-adaptive binary arithmetic coding. His Depth map study combines topics from a wide range of disciplines, such as Image based, Image conversion and Enhanced Data Rates for GSM Evolution. His work deals with themes such as Set top box, Virtual reality, Computer graphics and View synthesis, which intersect with Pixel.
This overview was generated by a machine learning system which analysed the scientist’s body of work. If you have any feedback, you can contact us here.
Efficient moving object segmentation algorithm using background registration technique
Shao-Yi Chien;Shyh-Yih Ma;Liang-Gee Chen.
IEEE Transactions on Circuits and Systems for Video Technology (2002)
Analysis, fast algorithm, and VLSI architecture design for H.264/AVC intra frame coder
Yu-Wen Huang;Bing-Yu Hsieh;Tung-Chien Chen;Liang-Gee Chen.
IEEE Transactions on Circuits and Systems for Video Technology (2005)
Analysis and architecture design of an HDTV720p 30 frames/s H.264/AVC encoder
Tung-Chien Chen;Shao-Yi Chien;Yu-Wen Huang;Chen-Han Tsai.
IEEE Transactions on Circuits and Systems for Video Technology (2006)
Analysis and architecture design of variable block-size motion estimation for H.264/AVC
Ching-Yeh Chen;Shao-Yi Chien;Yu-Wen Huang;Tung-Chien Chen.
IEEE Transactions on Circuits and Systems I-regular Papers (2006)
Analysis and architecture design of block-coding engine for EBCOT in JPEG 2000
Chung-Jr Lian;Kuan-Fu Chen;Hong-Hui Chen;Liang-Gee Chen.
IEEE Transactions on Circuits and Systems for Video Technology (2003)
Flipping structure: an efficient VLSI architecture for lifting-based discrete wavelet transform
Chao-Tsung Huang;Po-Chih Tseng;Liang-Gee Chen.
IEEE Transactions on Signal Processing (2004)
Analysis and complexity reduction of multiple reference frames motion estimation in H.264/AVC
Yu-Wen Huang;Bing-Yu Hsieh;Shao-Yi Chien;Shyh-Yih Ma.
IEEE Transactions on Circuits and Systems for Video Technology (2006)
Survey on Block Matching Motion Estimation Algorithms and Architectures with New Results
Yu-Wen Huang;Ching-Yeh Chen;Chen-Han Tsai;Chun-Fu Shen.
signal processing systems (2006)
Efficient Depth Image Based Rendering with Edge Dependent Depth Filter and Interpolation
Wan-Yu Chen;Yu-Lin Chang;Shyh-Feng Lin;Li-Fu Ding.
international conference on multimedia and expo (2005)
One-dimensional full search motion estimation algorithm for video coding
M.-J. Chen;L.-G. Chen;T.-D. Chiueh.
IEEE Transactions on Circuits and Systems for Video Technology (1994)
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