2023 - Research.com Electronics and Electrical Engineering in United States Leader Award
2002 - IEEE Fellow For contributions to the power-aware design of digital circuits.
Kaushik Roy focuses on Electronic engineering, CMOS, Transistor, Electrical engineering and Electronic circuit. His studies deal with areas such as Threshold voltage, Low-power electronics and Leakage as well as Electronic engineering. His research in CMOS intersects with topics in Power, Process variation, Voltage, Integrated circuit and Integrated injection logic.
His Transistor study combines topics in areas such as Optoelectronics and Nanoelectronics. His research in Electrical engineering tackles topics such as Spin-transfer torque which are related to areas like Torque. In his research on the topic of Electronic circuit, Benchmark is strongly related with Algorithm.
Kaushik Roy mainly focuses on Electronic engineering, CMOS, Electrical engineering, Artificial intelligence and Electronic circuit. His Electronic engineering research integrates issues from Transistor, Voltage, Low-power electronics and Leakage. In his study, Cache is inextricably linked to Static random-access memory, which falls within the broad field of Leakage.
His CMOS study combines topics from a wide range of disciplines, such as Power, Integrated circuit design and Process variation. His Artificial intelligence research includes themes of Machine learning and Pattern recognition. His biological study spans a wide range of topics, including Very-large-scale integration and Circuit design.
His primary areas of study are Artificial intelligence, Artificial neural network, Spiking neural network, Deep learning and Pattern recognition. Kaushik Roy interconnects Computer architecture, Edge device, Contextual image classification, Multiplication and Efficient energy use in the investigation of issues within Artificial neural network. As a member of one scientific family, Kaushik Roy mostly works in the field of Efficient energy use, focusing on Energy and, on occasion, CMOS.
His study in Spiking neural network is interdisciplinary in nature, drawing from both Gradient descent, Neuromorphic engineering, Spike and Neuron. His work deals with themes such as Adversarial system, Bottleneck and Electronic engineering, which intersect with Robustness. His work deals with themes such as Spin-transfer torque and Torque, which intersect with Electronic engineering.
His main research concerns Artificial intelligence, Artificial neural network, Spiking neural network, Pattern recognition and Machine learning. Kaushik Roy has included themes like Crossbar switch, Spike, Non-volatile memory, Residual and Efficient energy use in his Artificial neural network study. The Spiking neural network study combines topics in areas such as Gradient descent, Neuromorphic engineering, MNIST database and Neuron.
The concepts of his CMOS study are interwoven with issues in Matrix multiplication and Resistive random-access memory. Kaushik Roy integrates many fields in his works, including Input/output and Electronic engineering. His Electronic engineering research includes themes of Mixed-signal integrated circuit, Noise power and Leakage.
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Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits
K. Roy;S. Mukhopadhyay;H. Mahmoodi-Meimand.
Proceedings of the IEEE (2003)
Gated-V/sub dd/: a circuit technique to reduce leakage in deep-submicron cache memories
Michael Powell;Se-Hyun Yang;Babak Falsafi;Kaushik Roy.
international symposium on low power electronics and design (2000)
Low power CMOS VLSI circuit design
Kaushik Roy;Sharat Prasad.
Low-Power Digital Signal Processing Using Approximate Adders
V. Gupta;D. Mohapatra;A. Raghunathan;K. Roy.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (2013)
A 32 kb 10T Sub-Threshold SRAM Array With Bit-Interleaving and Differential Read Scheme in 90 nm CMOS
Ik Joon Chang;Jae-Joon Kim;S.P. Park;K. Roy.
IEEE Journal of Solid-state Circuits (2009)
Modeling of failure probability and statistical design of SRAM array for yield enhancement in nanoscaled CMOS
S. Mukhopadhyay;H. Mahmoodi;K. Roy.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (2005)
A 32kb 10T Subthreshold SRAM Array with Bit-Interleaving and Differential Read Scheme in 90nm CMOS
Ik Joon Chang;Jae-Joon Kim;S.P. Park;K. Roy.
international solid-state circuits conference (2008)
A 160 mV Robust Schmitt Trigger Based Subthreshold SRAM
J.P. Kulkarni;K. Kim;K. Roy.
IEEE Journal of Solid-state Circuits (2007)
Analysis and characterization of inherent application resilience for approximate computing
Vinay K. Chippa;Srimat T. Chakradhar;Kaushik Roy;Anand Raghunathan.
design automation conference (2013)
IMPACT: imprecise adders for low-power approximate computing
Vaibhav Gupta;Debabrata Mohapatra;Sang Phill Park;Anand Raghunathan.
international symposium on low power electronics and design (2011)
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