World's Best Scientists 2026 revealed!

D-Index & Metrics

Electronics and Electrical Engineering

D-Index
31
Citations
4573
World Ranking
6533
National Ranking
2140

Overview

Hamid Mahmoodi is affiliated with San Francisco State University in the United States. Their research spans multiple disciplines within engineering and computer science, focusing primarily on electrical and electronic engineering as well as artificial intelligence.

The main fields of study covered in Mahmoodi's work include:

  • Engineering
  • Computer Science

Within these fields, the subfields of study frequently addressed are:

  • Electrical and Electronic Engineering
  • Artificial Intelligence
  • Hardware and Architecture
  • Biomedical Engineering
  • Computational Mathematics

Mahmoodi's research explores a range of technical topics and applications such as:

  • Advanced Memory and Neural Computing
  • Physical Unclonable Functions (PUFs) and Hardware Security
  • Integrated Circuits and Semiconductor Failure Analysis
  • Low-power high-performance VLSI design
  • Analog and Mixed-Signal Circuit Design
  • Adversarial Robustness in Machine Learning
  • Tensor decomposition and applications

Their recent publications include the following works:

  • "Energy-Efficient Ternary Multipliers Using CNT Transistors," 2020, Electronics
  • "Silicon validation of LUT-based logic-locked IP cores," 2022, Proceedings of the 59th ACM/IEEE Design Automation Conference
  • "Breaking the Design and Security Trade-off of Look-up-table-based Obfuscation," 2022, ACM Transactions on Design Automation of Electronic Systems
  • "Cyclic Sparsely Connected Architectures: From foundations to applications," 2021, IEEE Solid-State Circuits Magazine

Frequent collaborators in Mahmoodi's work include:

  • Houman Homayoun
  • Gaurav Kolhe
  • Tyler Sheaves
  • Setareh Rafatirad
  • Avesta Sasan

Publication venues where Mahmoodi has contributed include:

  • Electronics
  • Proceedings of the 59th ACM/IEEE Design Automation Conference
  • ACM Transactions on Design Automation of Electronic Systems
  • IEEE Solid-State Circuits Magazine

Best Publications

  • Modeling of failure probability and statistical design of SRAM array for yield enhancement in nanoscaled CMOS

    S. Mukhopadhyay;H. Mahmoodi;K. Roy

  • A process-tolerant cache architecture for improved yield in nanoscale technologies

    A. Agarwal;B.C. Paul;H. Mahmoodi;A. Datta

  • Ultra Low-Power Clocking Scheme Using Energy Recovery and Clock Gating

    H. Mahmoodi;V. Tirumalashetty;M. Cooke;K. Roy

  • Diode-footed domino: a leakage-tolerant high fan-in dynamic circuit design style

    H. Mahmoodi-Meimand;K. Roy

  • Estimation of delay variations due to random-dopant fluctuations in nanoscale CMOS circuits

    H. Mahmoodi;S. Mukhopadhyay;K. Roy

  • Statistical design and optimization of SRAM cell for yield enhancement

    S. Mukhopadhyay;H. Mahmoodi;K. Roy

  • Low-power scan design using first-level supply gating

    S. Bhunia;H. Mahmoodi;D. Ghosh;S. Mukhopadhyay

  • Computation sharing programmable FIR filter for low-power and high-performance applications

    Jongsun Park;Woopyo Jeong;H. Mahmoodi-Meimand;Yongtao Wang

  • Double-gate SOI devices for low-power and high-performance applications

    K. Roy;H. Mahmoodi;S. Mukhopadhyay;H. Ananthan

  • Modeling and Circuit Synthesis for Independently Controlled Double Gate FinFET Devices

    A. Datta;A. Goel;R.T. Cakici;H. Mahmoodi

  • A Low-Power SRAM Using Bit-Line Charge-Recycling

    Keejong Kim;H. Mahmoodi;K. Roy

  • Design of a Process Variation Tolerant Self-Repairing SRAM for Yield Enhancement in Nanoscaled CMOS

    S. Mukhopadhyay;Keejong Kim;H. Mahmoodi;K. Roy

  • Asymmetrically Doped FinFETs for Low-Power Robust SRAMs

    F. Moradi;S. K. Gupta;G. Panagopoulos;D. T. Wisland

  • Domino logic designs for high-performance and leakage-tolerant applications

    Farshad Moradi;Tuan Vu Cao;Elena I. Vatajelu;Ali Peiravi

  • Modeling and testing of SRAM for new failure mechanisms due to process variations in nanoscale CMOS

    Qikai Chen;H. Mahmoodi;S. Bhunia;K. Roy

  • Data-retention flip-flops for power-down applications

    H. Mahmoodi-Meimand;K. Roy

  • Energy recovery clocking scheme and flip-flops for ultra low-energy applications

    Matthew Cooke;Hamid Mahmoodi-Meimand;Kaushik Roy

  • A novel synthesis approach for active leakage power reduction using dynamic supply gating

    Swarup Bhunia;Nilanjan Banerjee;Qikai Chen;Hamid Mahmoodi

  • Reliable and self-repairing SRAM in nano-scale technologies using leakage and delay monitoring

    Saibal Mukhopadhyay;Kunhyuk Kang;Hamid Mahmoodi;Kaushik Roy

  • A novel high-performance and robust sense amplifier using independent gate control in sub-50-nm double-gate MOSFET

    S. Mukhopadhyay;H. Mahmoodi;K. Roy

  • Design of high performance sense amplifier using independent gate control in sub-50nm double-gate MOSFET

    S. Mukhopadhyay;H. Mahmoodi;K. Roy

  • High performance and low power domino logic using independent gate control in double-gate SOI MOSFETs

    H. Mahmoodi;S. Mukhopadhyay;K. Roy

Frequent Co-Authors

Kaushik Roy
Kaushik Roy Purdue University West Lafayette
Swarup Bhunia
Swarup Bhunia University of Florida
Saibal Mukhopadhyay
Saibal Mukhopadhyay Georgia Institute of Technology
Arijit Raychowdhury
Arijit Raychowdhury Georgia Institute of Technology
Ali Afzali-Kusha
Ali Afzali-Kusha University of Tehran
Bipul C. Paul
Bipul C. Paul GlobalFoundries (United States)
Keivan Navi
Keivan Navi Shahid Beheshti University
Sumeet Kumar Gupta
Sumeet Kumar Gupta Purdue University West Lafayette

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