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Computer Science

D-Index
38
Citations
5902
World Ranking
10264
National Ranking
4309

Overview

Kris Gaj is affiliated with George Mason University in the United States. Their research primarily focuses on areas within computer science, with a strong emphasis on cryptography and hardware architecture.

The main fields of study for Kris Gaj include:

  • Computer Science

Their work spans several subfields such as:

  • Artificial Intelligence
  • Information Systems
  • Computer Vision and Pattern Recognition
  • Hardware and Architecture
  • Computational Theory and Mathematics

Kris Gaj's research covers a variety of topics, notably:

  • Cryptography and Data Security
  • Cryptographic Implementations and Security
  • Coding theory and cryptography
  • Cryptography and Residue Arithmetic
  • Chaos-based Image/Signal Encryption
  • Quantum Computing Algorithms and Architecture
  • DNA and Biological Computing

Recent papers authored under Kris Gaj's research umbrella include:

  • High-Speed Hardware Architectures and FPGA Benchmarking of CRYSTALS-Kyber, NTRU, and Saber (2022, IEEE Transactions on Computers)
  • Hardware Accelerators for Digital Signature Algorithms Dilithium and FALCON (2023, IEEE Design and Test)
  • Engineering Practical Rank-Code-Based Cryptographic Schemes on Embedded Hardware. A Case Study on ROLLO (2022, IEEE Transactions on Computers)
  • Universal Gaussian elimination hardware for cryptographic purposes (2024, Journal of Cryptographic Engineering)
  • Lightweight Champions of the World: Side-Channel Resistant Open Hardware for Finalists in the NIST Lightweight Cryptography Standardization Process (2024, ACM Transactions on Embedded Computing Systems)

Kris Gaj frequently collaborates with several researchers including:

  • Kamyar Mohajerani
  • Duc Tri Nguyen
  • Viet B. Dang
  • Luke Beckwith
  • Abubakr Abdulgadir

Publication venues where Kris Gaj's work appears most often include:

  • Proceedings of the Great Lakes Symposium on VLSI 2022
  • IEEE Transactions on Computers
  • IEEE Design and Test
  • Journal of Cryptographic Engineering
  • ACM Transactions on Embedded Computing Systems

Best Publications

  • Very Compact FPGA Implementation of the AES Algorithm

    Paweł Chodowiec;Kris Gaj

  • Cryptographic Hardware and Embedded Systems - CHES 2009

    Christophe Clavier;Kris Gaj

  • An embedded true random number generator for FPGAs

    Paul Kohlbrenner;Kris Gaj

  • Comparison of the Hardware Performance of the AES Candidates Using Reconfigurable Hardware.

    Kris Gaj;Pawel Chodowiec

  • The Promise of High-Performance Reconfigurable Computing

    T. El-Ghazawi;E. El-Araby;Miaoqing Huang;K. Gaj

  • Fast Implementation and Fair Comparison of the Final Candidates for Advanced Encryption Standard Using Field Programmable Gate Arrays

    Kris Gaj;Pawel Chodowiec

  • Fair and comprehensive methodology for comparing hardware performance of fourteen round two SHA-3 candidates using FPGAs

    Kris Gaj;Ekawat Homsirikamol;Marcin Rogawski

  • Timing of Multi-Gigahertz Rapid Single Flux Quantum Digital Circuits

    Kris Gaj;Eby G. Friedman;Marc J. Feldman

  • FPGA and ASIC Implementations of AES

    Kris Gaj;Pawel Chodowiec

  • New Hardware Architectures for Montgomery Modular Multiplication Algorithm

    Miaoqing Huang;K Gaj;T El-Ghazawi

  • Comparative Analysis of the Hardware Implementations of Hash Functions SHA-1 and SHA-512

    Tim Grembowski;Roar Lien;Kris Gaj;Nghi Nguyen

  • Fast implementations of secret-key block ciphers using mixed inner- and outer-round pipelining

    Pawel Chodowiec;Po Khuon;Kris Gaj

  • A Configurable Ring-Oscillator-Based PUF for Xilinx FPGAs

    Xin Xin;Jens-Peter Kaps;Kris Gaj

  • ATHENa - Automated Tool for Hardware EvaluatioN: Toward Fair and Comprehensive Benchmarking of Cryptographic Hardware Using FPGAs

    Kris Gaj;Jens-Peter Kaps;Venkata Amirineni;Marcin Rogawski

  • Guest Editors' Introduction: High-Performance Reconfigurable Computing

    Duncan Buell;Tarek El-Ghazawi;Kris Gaj;Volodymyr Kindratenko

  • LUT-Lock: A Novel LUT-Based Logic Obfuscation for FPGA-Bitstream and ASIC-Hardware Protection

    Hadi Mardani Kamali;Kimia Zamiri Azar;Kris Gaj;Houman Homayoun

  • Tools for the computer-aided design of multigigahertz superconducting digital circuits

    K. Gaj;Q.P. Herr;V. Adler;A. Krasniewski

  • Comprehensive Evaluation of High-Speed and Medium-Speed Implementations of Five SHA-3 Finalists Using Xilinx and Altera FPGAs.

    Kris Gaj;Ekawat Homsirikamol;Marcin Rogawski;Rabia Shahid

  • A 1 Gbit/s Partially Unrolled Architecture of Hash Functions SHA-1 and SHA-512

    Roar Lien;Tim Grembowski;Kris Gaj

  • Experimental Testing of the Gigabit IPSec-Compliant Implementations of Rijndael and Triple DES Using SLAAC-1V FPGA Accelerator Board

    Pawel Chodowiec;Kris Gaj;Peter Bellows;Brian Schott

  • Comparing Hardware Performance of Fourteen Round Two SHA-3 Candidates Using FPGAs.

    Ekawat Homsirikamol;Marcin Rogawski;Kris Gaj

Frequent Co-Authors

Tarek El-Ghazawi
Tarek El-Ghazawi George Washington University
Eby G. Friedman
Eby G. Friedman University of Rochester
Josef Pieprzyk
Josef Pieprzyk Commonwealth Scientific and Industrial Research Organisation
Hamid Mahmoodi
Hamid Mahmoodi San Francisco State University
Russell Tessier
Russell Tessier University of Massachusetts Amherst
Viktor K. Prasanna
Viktor K. Prasanna University of Southern California
Huaxiong Wang
Huaxiong Wang Nanyang Technological University

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