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Jean-Luc Danger

Jean-Luc Danger

D-Index & Metrics

Electronics and Electrical Engineering

D-Index
34
Citations
4114
World Ranking
5877
National Ranking
118

Overview

Jean-Luc Danger is affiliated with Télécom ParisTech in France and has made significant contributions to the fields of computer science and engineering. Their research primarily spans areas such as artificial intelligence, hardware and architecture, and electrical and electronic engineering.

Their work covers a variety of topics with a concentration on physical unclonable functions (PUFs) and hardware security, cryptographic implementations and security, and advanced malware detection techniques. Other research interests include integrated circuits and semiconductor failure analysis, chaos-based image and signal encryption, security and verification in computing, and neuroscience and neural engineering.

Jean-Luc Danger has frequently collaborated with several researchers, including Sylvain Guilley, Naghmeh Karimi, Wei Cheng, Ulrich Kühne, and Michael Pehl.

Their research has been published in numerous venues, with a particular presence in:

  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
  • IEEE Transactions on Information Forensics and Security
  • Journal of Electronic Testing
  • Microelectronics Reliability
  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Selected recent papers by Jean-Luc Danger include:

  • Side channel attacks for architecture extraction of neural networks, 2021, CAAI Transactions on Intelligence Technology
  • Unsupervised Network Intrusion Detection System for AVTP in Automotive Ethernet Networks, 2022, 2022 IEEE Intelligent Vehicles Symposium (IV)
  • Detecting Failures and Attacks via Digital Sensors, 2020, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
  • Information Leakages in Code-based Masking: A Unified Quantification Approach, 2021, IACR Transactions on Cryptographic Hardware and Embedded Systems
  • Diffusional Side-Channel Leakage From Unrolled Lightweight Block Ciphers: A Case Study of Power Analysis on PRINCE, 2020, IEEE Transactions on Information Forensics and Security

Best Publications

  • Lambda-Min Decoding Algorithm of Regular and Irregular LDPC Codes

    Frédéric Guilloud;Emmanuel Boutillon;Jean-Luc Danger

  • An Easy-to-Design PUF Based on a Single Oscillator: The Loop PUF

    Zouha Cherif;Jean-Luc Danger;Sylvain Guilley;Lilian Bossuet

  • Linear complementary dual code improvement to strengthen encoded circuit against hardware Trojan horses

    Xuan Thuy Ngo;Shivam Bhasin;Jean-Luc Danger;Sylvain Guilley

  • Analysis of Electromagnetic Information Leakage From Cryptographic Devices With Different Physical Structures

    Y. Hayashi;N. Homma;T. Mizuki;T. Aoki

  • Wavelet transform based pre-processing for side channel analysis

    Nicolas Debande;Youssef Souissi;M. Abdelaziz El Aabid;Sylvain Guilley

  • Design of High Speed AWGN Communication Channel Emulator

    Unknown

  • Generic Description and Synthesis of LDPC Decoders

    Unknown

  • Cryptographically secure shields

    Jean-Michel Cioranesco;Jean-Luc Danger;Tarik Graba;Sylvain Guilley

  • Hardware property checker for run-time Hardware Trojan detection

    Xuan Thuy Ngo;Jean-Luc Danger;Sylvain Guilley;Zakaria Najm

  • Laser-induced Single-bit Faults in Flash Memory: Instructions Corruption on a 32-bit Microcontroller

    Brice Colombier;Alexandre Menu;Jean-Max Dutertre;Pierre-Alain Moellic

  • Cryptographically Secure Shield for Security IPs Protection

    Xuan Thuy Ngo;Jean-Luc Danger;Sylvain Guilley;Tarik Graba

  • Silicon-level Solutions to Counteract Passive and Active Attacks

    S. Guilley;L. Sauvage;J.-L. Danger;N. Selmane

  • Fault Injection Resilience

    Sylvain Guilley;Laurent Sauvage;Jean-Luc Danger;Nidhal Selmane

  • Leakage squeezing countermeasure against high-order attacks

    Houssem Maghrebi;Sylvain Guilley;Jean-Luc Danger

  • High Throughput/Gate AES Hardware Architectures Based on Datapath Compression

    Rei Ueno;Naofumi Homma;Sumio Morioka;Noriyuki Miura

  • PLL to the rescue: a novel EM fault countermeasure

    Noriyuki Miura;Zakaria Najm;Wei He;Shivam Bhasin

  • Successful attack on an FPGA-based WDDL DES cryptoprocessor without place and route constraints

    Laurent Sauvage;Sylvain Guilley;Jean-Luc Danger;Yves Mathieu

  • Countering early evaluation: an approach towards robust dual-rail precharge logic

    Shivam Bhasin;Sylvain Guilley;Florent Flament;Nidhal Selmane

  • Practical improvements of side-channel attacks on AES: feedback from the 2nd DPA contest

    Christophe Clavier;Jean-Luc Danger;Guillaume Duc;M. Abdelaziz Elaabid

  • Side channel attacks for architecture extraction of neural networks

    Hervé Chabanne;Jean-Luc Danger;Linda Guiga;Ulrich Kühne

  • Achieving side-channel high-order correlation immunity with leakage squeezing

    Claude Carlet;Jean-Luc Danger;Sylvain Guilley;Houssem Maghrebi;Houssem Maghrebi

  • Unrolling cryptographic circuits: a simple countermeasure against side-channel attacks

    Shivam Bhasin;Sylvain Guilley;Laurent Sauvage;Jean-Luc Danger

  • Security evaluation of application-specific integrated circuits and field programmable gate arrays against setup time violation attacks

    Nidhal Selmane;Shivam Bhasin;Sylvain Guilley;Jean-Luc Danger

  • Dismantling Real-World ECC with Horizontal and Vertical Template Attacks

    Margaux Dugardin;Margaux Dugardin;Louiza Papachristodoulou;Zakaria Najm;Lejla Batina

  • Far correlation-based EMA with a precharacterized leakage model

    Olivier Meynard;Sylvain Guilley;Jean-Luc Danger;Laurent Sauvage

Frequent Co-Authors

Ioannis Krikidis
Ioannis Krikidis University of Cyprus

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