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Computer Science

D-Index
39
Citations
6779
World Ranking
9730
National Ranking
4111

Electronics and Electrical Engineering

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39
Citations
6725
World Ranking
4678
National Ranking
1645

Overview

Russell Tessier is affiliated with the University of Massachusetts Amherst in the United States. Their research primarily focuses on computer science and engineering, with significant contributions in hardware and architecture, artificial intelligence, and electrical and electronic engineering. Additional areas of study include computer networks and communications, and signal processing.

The scientist's work covers several main topics, including:

  • Physical Unclonable Functions (PUFs) and Hardware Security
  • Cryptographic Implementations and Security
  • Security and Verification in Computing
  • Radiation Effects in Electronics
  • Advanced Memory and Neural Computing
  • Integrated Circuits and Semiconductor Failure Analysis
  • Advanced Malware Detection Techniques

Russell Tessier has published extensively in multiple venues. The most frequent publication outlets include:

  • ACM Transactions on Reconfigurable Technology and Systems
  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems
  • Proceedings of the IEEE
  • ACM Transactions on Embedded Computing Systems
  • IACR Transactions on Cryptographic Hardware and Embedded Systems

Recent papers by Tessier illustrate ongoing research in FPGA acceleration, hardware security, and power-related attacks in multi-tenant environments. Selected recent publications include:

  • "The Future of FPGA Acceleration in Datacenters and the Cloud," 2022, ACM Transactions on Reconfigurable Technology and Systems
  • "Power Distribution Attacks in Multitenant FPGAs," 2020, IEEE Transactions on Very Large Scale Integration (VLSI) Systems
  • "Mitigating Voltage Attacks in Multi-Tenant FPGAs," 2021, ACM Transactions on Reconfigurable Technology and Systems
  • "Voltage Sensor Implementations for Remote Power Attacks on FPGAs," 2022, ACM Transactions on Reconfigurable Technology and Systems
  • "Jitter-based Adaptive True Random Number Generation Circuits for FPGAs in the Cloud," 2022, ACM Transactions on Reconfigurable Technology and Systems

Collaboration is a notable aspect of Tessier's research environment, with frequent co-authors including George Provelengios, Daniel Holcomb, Jakub Szefer, Shayan Moini, and Xiang Li. These collaborations reflect ongoing interdisciplinary and applied approaches within the fields of FPGA technology and hardware security.

Best Publications

  • FPGA Architecture: Survey and Challenges

    Ian Kuon;Russell Tessier;Jonathan Rose

  • Reconfigurable Computing for Digital Signal Processing: A Survey

    Russell Tessier;Wayne Burleson

  • Virtual interconnections for reconfigurable logic systems

    Anant Agarwal;Jonathan Babb;Russell Tessier

  • aSOC: A Scalable, Single-Chip Communications Architecture

    Jian Liang;Sriram Swaminathan;Russell Tessier

  • Reconfigurable Computing Architectures

    Russell Tessier;Kenneth Pocek;Andre DeHon

  • Virtual wires: overcoming pin limitations in FPGA-based logic emulators

    J. Babb;R. Tessier;A. Agarwal

  • Logic emulation with virtual wires

    J. Babb;R. Tessier;M. Dahl;S.Z. Hanono

  • A MATLAB compiler for distributed, heterogeneous, reconfigurable computing systems

    P. Banerjee;N. Shenoy;A. Choudhary;S. Hauck

  • Balancing Logic Utilization and Area Efficiency in FPGAs

    Russell Tessier;Heather Giza

  • Floating point unit generation and evaluation for FPGAs

    Jian Liang;R. Tessier;O. Mencer

  • FPGA Side Channel Attacks without Physical Access

    Chethan Ramesh;Shivukumar B. Patil;Siva Nishok Dhanuskodi;George Provelengios

  • An architecture and compiler for scalable on-chip communication

    Jian Liang;A. Laffely;S. Srinivasan;R. Tessier

  • A dynamically reconfigurable adaptive viterbi decoder

    Sriram Swaminathan;Russell Tessier;Dennis Goeckel;Wayne Burleson

  • Trading off transient fault tolerance and power consumption in deep submicron (DSM) VLSI circuits

    A. Maheshwari;W. Burleson;R. Tessier

  • Tolerating operational faults in cluster-based FPGAs

    Vijay Lakamraju;Russell Tessier

  • BDD-based logic synthesis for LUT-based FPGAs

    Navin Vemuri;Priyank Kalla;Russell Tessier

  • FlexGrip: A soft GPGPU for FPGAs

    Kevin Andryc;Murtaza Merchant;Russell Tessier

  • Emulation of the Sparcle microprocessor with the MIT Virtual Wires emulation system

    M. Dahl;J. Babb;R. Tessier;S. Hanono

  • Multicore soft error rate stabilization using adaptive dual modular redundancy

    Ramakrishna Vadlamani;Jia Zhao;Wayne Burleson;Russell Tessier

  • BIST-based delay path testing in FPGA architectures

    I.G. Harris;P.R. Menon;R. Tessier

  • Testing and diagnosis of interconnect faults in cluster-based FPGA architectures

    I.G. Harris;R. Tessier

Frequent Co-Authors

Wayne Burleson
Wayne Burleson University of Massachusetts Amherst
Lixin Gao
Lixin Gao University of Massachusetts Amherst
Christof Paar
Christof Paar Max Planck Institute for Security and Privacy
Dennis Goeckel
Dennis Goeckel University of Massachusetts Amherst
Vaughn Betz
Vaughn Betz University of Toronto
André DeHon
André DeHon University of Pennsylvania
Jonathan Rose
Jonathan Rose University of Toronto
Scott Hauck
Scott Hauck University of Washington
Subbu S. Venkatraman
Subbu S. Venkatraman National University of Singapore

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