World's Best Scientists 2026 revealed!

D-Index & Metrics

Computer Science

D-Index
70
Citations
17043
World Ranking
1895
National Ranking
110

Electronics and Electrical Engineering

D-Index
68
Citations
15658
World Ranking
1034
National Ranking
48

Research.com Recognitions

  • 2012 - Fellow of the Royal Academy of Engineering (UK)

Overview

Wayne Luk is affiliated with Imperial College London in the United Kingdom. Their research is predominantly situated within the field of Computer Science, with a strong focus on subfields such as Artificial Intelligence, Computer Vision and Pattern Recognition, Electrical and Electronic Engineering, Hardware and Architecture, and Computer Networks and Communications.

The scientist's work covers a range of topics including:

  • Advanced Neural Network Applications
  • Parallel Computing and Optimization Techniques
  • Adversarial Robustness in Machine Learning
  • CCD and CMOS Imaging Sensors
  • Advanced Memory and Neural Computing
  • Embedded Systems Design Techniques
  • Fault Detection and Control Systems

Wayne Luk has published extensively, contributing to scientific literature in notable venues. Frequent publication venues include:

  • arXiv (Cornell University)
  • Proceedings on CD-ROM - International Society for Magnetic Resonance in Medicine. Scientific Meeting and Exhibition/Proceedings of the International Society for Magnetic Resonance in Medicine, Scientific Meeting and Exhibition
  • IEEE Transactions on Neural Networks and Learning Systems
  • Journal of Signal Processing Systems
  • IEEE Transactions on Parallel and Distributed Systems

Some recent papers authored by Wayne Luk include:

  • FPGA-Based Acceleration for Bayesian Convolutional Neural Networks, 2022, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
  • Toward Full-Stack Acceleration of Deep Convolutional Neural Networks on FPGAs, 2021, IEEE Transactions on Neural Networks and Learning Systems
  • LhARA: The Laser-hybrid Accelerator for Radiobiological Applications, 2020, Frontiers in Physics
  • Mapping Large LSTMs to FPGAs with Weight Reuse, 2020, Journal of Signal Processing Systems
  • Towards efficient deep neural network training by FPGA-based batch-level parallelism, 2020, Journal of Semiconductors

The scientist has worked with several frequent collaborators, including Hongxiang Fan, Zhiqiang Que, Ce Guo, Martin Ferianc, and Xinyu Niu. These collaborations appear across multiple studies and publications.

Wayne Luk was recognized as a Fellow of the Royal Academy of Engineering (UK) in 2012. This acknowledges a distinguished level of professional contribution within their field.

Best Publications

  • Reconfigurable computing: architectures and design methods

    T.J. Todman;G.A. Constantinides;S.J.E. Wilton;O. Mencer

  • Gaussian random number generators

    David B. Thomas;Wayne Luk;Philip H.W. Leong;John D. Villasenor

  • Accuracy-Guaranteed Bit-Width Optimization

    D.-U. Lee;A.A. Gaffar;R.C.C. Cheung;O. Mencer

  • Pipeline vectorization

    M. Weinhardt;W. Luk

  • A comparison of CPUs, GPUs, FPGAs, and massively parallel processor arrays for random number generation

    David Barrie Thomas;Lee Howes;Wayne Luk

  • A hardware Gaussian noise generator using the Box-Muller method and its error analysis

    D.-U. Lee;J.D. Villasenor;W. Luk;P.H.W. Leong

  • Axel: a heterogeneous cluster with FPGAs and GPUs

    Kuen Hung Tsoi;Wayne Luk

  • FP-BNN

    Shuang Liang;Shouyi Yin;Leibo Liu;Wayne Luk

  • Comparing Three Heuristic Search Methods for Functional Partitioning in Hardware–Software Codesign

    Theerayod Wiangtong;Peter Y. Cheung;Wayne Luk

  • Flexible instruction processor systems and methods

    Wayne Luk;Peter Y. K. Cheung;Shay Ping Seng

  • Wordlength optimization for linear digital signal processing

    G.A. Constantinides;P.Y.K. Cheung;W. Luk

  • Compilation tools for run-time reconfigurable designs

    W. Luk;N. Shirazi;P.Y.K. Cheung

  • Pipeline vectorization for reconfigurable systems

    M. Weinhardt;W. Luk

  • Unifying bit-width optimisation for fixed-point and floating-point designs

    A.A. Gaffar;O. Mencer;W. Luk

  • Dynamic voltage scaling for commercial FPGAs

    C.T. Chow;L.S.M. Tsui;P.H.W. Leong;W. Luk

  • Performance Comparison of Graphics Processors to Reconfigurable Logic: A Case Study

    B. Cope;P.Y.K. Cheung;W. Luk;L. Howes

  • The Impact of Pipelining on Energy per Operation in Field-Programmable Gate Arrays

    Steven J. E. Wilton;Su-Shin Ang;Wayne Luk

  • Floating-point bitwidth analysis via automatic differentiation

    A.A. Gaffar;O. Mencer;W. Luk;P.Y.K. Cheung

  • Enhancing Relocatability of Partial Bitstreams for Run-Time Reconfiguration

    T. Becker;W. Luk;P.Y.K. Cheung

  • A hardware Gaussian noise generator using the Wallace method

    Dong-U Lee;W. Luk;J.D. Villasenor;Guanglie Zhang

Frequent Co-Authors

Peter Y. K. Cheung
Peter Y. K. Cheung Imperial College London
George A. Constantinides
George A. Constantinides Imperial College London
Philip H. W. Leong
Philip H. W. Leong University of Sydney
Steven J. E. Wilton
Steven J. E. Wilton University of British Columbia
Guangwen Yang
Guangwen Yang Tsinghua University
Koen Bertels
Koen Bertels Delft University of Technology
Donatella Sciuto
Donatella Sciuto Polytechnic University of Milan
Jan Maciejowski
Jan Maciejowski University of Cambridge
Naranker Dulay
Naranker Dulay Imperial College London
Emil Lupu
Emil Lupu Imperial College London

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