World's Best Scientists 2026 revealed!

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Computer Science

D-Index
39
Citations
7402
World Ranking
9673
National Ranking
382

Electronics and Electrical Engineering

D-Index
39
Citations
7399
World Ranking
4639
National Ranking
213

Research.com Recognitions

  • 2006 - ACM Senior Member

Overview

Steven J. E. Wilton is affiliated with the University of British Columbia in Canada. Their research spans multiple fields and subfields of study, primarily focusing on Computer Science and Engineering. Within these domains, the scientist has contributed significantly to Electrical and Electronic Engineering, Artificial Intelligence, and Hardware and Architecture, with additional work related to Computer Vision and Pattern Recognition as well as Computer Networks and Communications.

The main topics addressed in their research include low-power high-performance VLSI design, VLSI and analog circuit testing, VLSI and FPGA design techniques, parallel computing and optimization techniques, embedded systems design techniques, ferroelectric and negative capacitance devices, and neural networks and applications.

Steven J. E. Wilton's publications are found in various esteemed venues. The most frequent publication venues include arXiv (Cornell University), with six papers; ACM Transactions on Reconfigurable Technology and Systems, with five papers; Journal of Algorithms & Computational Technology; and the Journal of Systems Architecture.

Their recent papers exemplify the focus and diversity of research topics:

  • Automatic High-quality Verilog Assertion Generation through Subtask-Focused Fine-Tuned LLMs and Iterative Prompting (2024, arXiv)
  • FPGA Architecture Exploration for DNN Acceleration (2022, ACM Transactions on Reconfigurable Technology and Systems)
  • Using data-mining techniques to improve combinatorial optimization algorithms (2022, Journal of Algorithms & Computational Technology)
  • Rethinking Embedded Blocks for Machine Learning Applications (2021, ACM Transactions on Reconfigurable Technology and Systems)
  • Fast Turnaround HLS Debugging Using Dependency Analysis and Debug Overlays (2020, ACM Transactions on Reconfigurable Technology and Systems)

The scientist collaborates frequently with a consistent group of coauthors, including Lesley Shannon, Behnam Ghavami, Esther Roorda, Mohammad Shahidzadeh, and S A Rasoulinezhad.

Steven J. E. Wilton was recognized in 2006 with the ACM Senior Member award, reflecting a longstanding presence in their research community.

Best Publications

  • CACTI: an enhanced cache access and cycle time model

    S.J.E. Wilton;N.P. Jouppi

  • Reconfigurable computing: architectures and design methods

    T.J. Todman;G.A. Constantinides;S.J.E. Wilton;O. Mencer

  • An Enhanced Access and Cycle Time Model for On-Chip Caches

    Steven J.E. Wilton;Norman P. Jouppi

  • System-on-Chip: Reuse and Integration

    R. Saleh;S. Wilton;S. Mirabbasi;A. Hu

  • A detailed power model for field-programmable gate arrays

    Kara K. W. Poon;Steven J. E. Wilton;Andy Yan

  • Architectures and algorithms for field-programmable gate arrays with embedded memory

    Jonathan Rose;Zvenko Vranesic;Steven Joseph Edward Wilton

  • A Flexible Power Model for FPGAs

    Kara K. W. Poon;Andy Yan;Steven J. E. Wilton

  • Tradeoffs in two-level on-chip caching

    N. P. Jouppi;S. J. E. Wilton

  • On the Interaction Between Power-Aware FPGA CAD Algorithms

    Julien Lamoureux;Steven J. E. Wilton

  • Dynamic voltage scaling for commercial FPGAs

    C.T. Chow;L.S.M. Tsui;P.H.W. Leong;W. Luk

  • The Impact of Pipelining on Energy per Operation in Field-Programmable Gate Arrays

    Steven J. E. Wilton;Su-Shin Ang;Wayne Luk

  • Memory-to-memory connection structures in FPGAs with embedded memory arrays

    Steven J. E. Wilton;Jonathan Rose;Zvonko G. Vranesic

  • Activity Estimation for Field-Programmable Gate Arrays

    Julien Lamoureux;Steven Wilton

  • BackSpace: Formal Analysis for Post-Silicon Debug

    F.M. De Paula;M. Gort;A.J. Hu;S. Wilton

  • Floating-Point FPGA: Architecture and Modeling

    Chun Hok Ho;Chi Wai Yu;P. Leong;W. Luk

  • Programmable logic IP cores in SoC design: opportunities and challenges

    S.J.E. Wilton;R. Saleh

  • A New Switch Block for Segmented FPGAs

    M. Imran Masud;Steven J. E. Wilton

  • SMAP: heterogeneous technology mapping for area reduction in FPGAs with embedded memory arrays

    Steven J. E. Wilton

  • An energy and power consumption analysis of FPGA routing architectures

    Peter Jamieson;Wayne Luk;Steve J.E. Wilton;George A. Constantinides

  • Virtual Embedded Blocks: A Methodology for Evaluating Embedded Elements in FPGAs

    C.h. Ho;P.h.w. Leong;W. Luk;S.J.E. Wilton

Frequent Co-Authors

Wayne Luk
Wayne Luk Imperial College London
Philip H. W. Leong
Philip H. W. Leong University of Sydney
Jonathan Rose
Jonathan Rose University of Toronto
Alan J. Hu
Alan J. Hu University of British Columbia
Resve Saleh
Resve Saleh University of British Columbia
Andre Ivanov
Andre Ivanov University of British Columbia
Norman P. Jouppi
Norman P. Jouppi Google (United States)
Rabab K. Ward
Rabab K. Ward University of British Columbia
Peter Y. K. Cheung
Peter Y. K. Cheung Imperial College London
George A. Constantinides
George A. Constantinides Imperial College London

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