2006 - ACM Senior Member
Steven J. E. Wilton mainly investigates Embedded system, Field-programmable gate array, Reconfigurable computing, Routing and Computer architecture. His Embedded system study integrates concerns from other disciplines, such as Block, Computer hardware and Overhead. His Field-programmable gate array research incorporates elements of Electronic circuit and Electronic engineering.
His Reconfigurable computing research integrates issues from Simulation, Short circuit, Integrated circuit, Variety and Power model. His Computer architecture study combines topics in areas such as Programmable logic array, Programmable logic device, Programmable Array Logic, Microprocessor and Simple programmable logic device. His Algorithm research focuses on Interleaved memory and how it connects with Parallel computing.
Field-programmable gate array, Embedded system, Computer architecture, Programmable logic device and Programmable logic array are his primary areas of study. His research in Field-programmable gate array intersects with topics in Routing, Electronic circuit and Parallel computing, Benchmark. His Embedded system study combines topics from a wide range of disciplines, such as Debugging and Integrated circuit.
The various areas that he examines in his Computer architecture study include Computing with Memory and Design flow. His studies deal with areas such as Logic synthesis, Logic family and System bus as well as Programmable logic device. The Programmable logic array study combines topics in areas such as Programmable Array Logic, Erasable programmable logic device, Macrocell array, Complex programmable logic device and Simple programmable logic device.
His main research concerns Field-programmable gate array, Embedded system, Debugging, Instrumentation and Software. Steven J. E. Wilton specializes in Field-programmable gate array, namely High-level synthesis. Steven J. E. Wilton works mostly in the field of High-level synthesis, limiting it down to concerns involving Compiler and, occasionally, Cache, Cycles per instruction, Parallel computing and Speedup.
His work on System on a chip as part of general Embedded system study is frequently linked to Work, therefore connecting diverse disciplines of science. His study in Software is interdisciplinary in nature, drawing from both Multiprocessing, Hardware description language and Direct memory access. The study incorporates disciplines such as Python, Computer architecture and Gate array in addition to Deep learning.
The scientist’s investigation covers issues in Field-programmable gate array, Embedded system, Debugging, High-level synthesis and Software. Steven J. E. Wilton integrates many fields, such as Field-programmable gate array and Visibility, in his works. Steven J. E. Wilton works in the field of Embedded system, namely Reconfigurable computing.
His studies in Instrumentation integrate themes in fields like Computer architecture and Debug menu. Steven J. E. Wilton has included themes like System on a chip and Instruction set in his Software bug study. The concepts of his Computation study are interwoven with issues in Python and Artificial neural network, Deep learning, Artificial intelligence.
This overview was generated by a machine learning system which analysed the scientist’s body of work. If you have any feedback, you can contact us here.
CACTI: an enhanced cache access and cycle time model
S.J.E. Wilton;N.P. Jouppi.
IEEE Journal of Solid-state Circuits (1996)
CACTI: an enhanced cache access and cycle time model
S.J.E. Wilton;N.P. Jouppi.
IEEE Journal of Solid-state Circuits (1996)
Reconfigurable computing: architectures and design methods
T.J. Todman;G.A. Constantinides;S.J.E. Wilton;O. Mencer.
IEE Proceedings - Computers and Digital Techniques (2005)
Reconfigurable computing: architectures and design methods
T.J. Todman;G.A. Constantinides;S.J.E. Wilton;O. Mencer.
IEE Proceedings - Computers and Digital Techniques (2005)
An Enhanced Access and Cycle Time Model for On-Chip Caches
Steven J.E. Wilton;Norman P. Jouppi.
(1999)
An Enhanced Access and Cycle Time Model for On-Chip Caches
Steven J.E. Wilton;Norman P. Jouppi.
(1999)
System-on-Chip: Reuse and Integration
R. Saleh;S. Wilton;S. Mirabbasi;A. Hu.
Proceedings of the IEEE (2006)
System-on-Chip: Reuse and Integration
R. Saleh;S. Wilton;S. Mirabbasi;A. Hu.
Proceedings of the IEEE (2006)
A detailed power model for field-programmable gate arrays
Kara K. W. Poon;Steven J. E. Wilton;Andy Yan.
ACM Transactions on Design Automation of Electronic Systems (2005)
A detailed power model for field-programmable gate arrays
Kara K. W. Poon;Steven J. E. Wilton;Andy Yan.
ACM Transactions on Design Automation of Electronic Systems (2005)
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