2020 - Fellow, National Academy of Inventors
2019 - Semiconductor Industry Association University Researcher Award
2017 - Member of the National Academy of Engineering For pioneering contributions to application-specific programmable logic via innovations in field-programmable gate array synthesis.
2008 - ACM Fellow For contributions to electronic design automation.
2001 - IEEE Fellow For contributions to the computer-aided design of integrated circuits, especially in physical design automation, interconnect optimization, and synthesis of field-programmable gate-arrays.
The scientist’s investigation covers issues in Field-programmable gate array, Embedded system, Parallel computing, Routing and Algorithm. The various areas that Jason Cong examines in his Field-programmable gate array study include Computer architecture, Electronic circuit, Application-specific integrated circuit, Lookup table and Logic synthesis. His work in Embedded system addresses subjects such as Software, which are connected to disciplines such as Scheduling.
His work in Parallel computing addresses issues such as Scalability, which are connected to fields such as Interconnection, Hierarchy, Bottleneck, Process and Computer engineering. His studies deal with areas such as Mathematical optimization, Steiner tree problem, RC time constant and Elmore delay as well as Routing. His Algorithm research is multidisciplinary, relying on both Graph, Netlist, Theoretical computer science and Benchmark.
Jason Cong mostly deals with Field-programmable gate array, Parallel computing, Embedded system, Algorithm and Routing. His Field-programmable gate array research incorporates elements of Lookup table, Logic synthesis, Computer architecture and Speedup. His work deals with themes such as Scheduling, Scalability, Interconnection and Electronic circuit, which intersect with Parallel computing.
The various areas that Jason Cong examines in his Embedded system study include Software, Efficient energy use and Multi-core processor. The Algorithm study combines topics in areas such as Very-large-scale integration and Mathematical optimization, Minification. Much of his study explores Routing relationship to Steiner tree problem.
His primary areas of investigation include Field-programmable gate array, Embedded system, Parallel computing, Speedup and Software. Particularly relevant to High-level synthesis is his body of work in Field-programmable gate array. His High-level synthesis research is multidisciplinary, incorporating elements of Correctness and Benchmark.
His Embedded system study deals with Dram intersecting with Cache. The study incorporates disciplines such as Systolic array, Compiler and Stencil in addition to Parallel computing. The concepts of his Speedup study are interwoven with issues in Memory hierarchy and Artificial intelligence.
Field-programmable gate array, Embedded system, Parallel computing, Efficient energy use and Computer architecture are his primary areas of study. His Field-programmable gate array research is multidisciplinary, incorporating perspectives in Latency, Computer engineering, Key, Bottleneck and Computation. Jason Cong interconnects Automation and Software in the investigation of issues within Embedded system.
His Parallel computing study integrates concerns from other disciplines, such as Scalability and Porting. His Efficient energy use study combines topics in areas such as Distributed computing, Computational complexity theory, Cluster, Dynamic programming and FPGA prototype. His Computer architecture research incorporates themes from High-level synthesis and Artificial neural network, Deep learning, Convolutional neural network, Artificial intelligence.
This overview was generated by a machine learning system which analysed the scientist’s body of work. If you have any feedback, you can contact us here.
Optimizing FPGA-based Accelerator Design for Deep Convolutional Neural Networks
Chen Zhang;Peng Li;Guangyu Sun;Yijin Guan.
field programmable gate arrays (2015)
An optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs
Jason Cong;Yuzheng Ding.
international conference on computer aided design (1992)
High-Level Synthesis for FPGAs: From Prototyping to Deployment
Jason Cong;Bin Liu;Stephen Neuendorffer;Juanjo Noguera.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (2011)
A thermal-driven floorplanning algorithm for 3D ICs
J. Cong;Jie Wei;Yan Zhang.
international conference on computer aided design (2004)
Performance optimization of VLSI interconnect layout
Jason Cong;Lei He;Cheng-Kok Koh;Patrick H. Madden.
CMP network-on-chip overlaid with multi-band RF-interconnect
M.F. Chang;J. Cong;A. Kaplan;M. Naik.
high-performance computer architecture (2008)
Application-specific instruction generation for configurable processor architectures
Jason Cong;Yiping Fan;Guoling Han;Zhiru Zhang.
field programmable gate arrays (2004)
Caffeine: Toward Uniformed Representation and Acceleration for Deep Convolutional Neural Networks
Chen Zhang;Guangyu Sun;Zhenman Fang;Peipei Zhou.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (2019)
Combinational logic synthesis for LUT based field programmable gate arrays
Jason Cong;Yuzheng Ding.
ACM Transactions on Design Automation of Electronic Systems (1996)
An interconnect-centric design flow for nanometer technologies
Proceedings of the IEEE (2001)
If you think any of the details on this page are incorrect, let us know.
We appreciate your kind effort to assist us to improve this page, it would be helpful providing us with as much detail as possible in the text box below: