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D-Index & Metrics

Electronics and Electrical Engineering

D-Index
54
Citations
10433
World Ranking
2305
National Ranking
898

Overview

Sung Kyu Lim is affiliated with Georgia Institute of Technology in the United States. Their research contributions predominantly lie within the fields of Engineering and Computer Science, with a focus on Electrical and Electronic Engineering, Hardware and Architecture, Computer Networks and Communications, Computer Vision and Pattern Recognition, and Artificial Intelligence.

Their work addresses various key topics including 3D IC and TSV technologies, VLSI and FPGA design techniques, advanced memory and neural computing, ferroelectric and negative capacitance devices, semiconductor materials and devices, VLSI and analog circuit testing, and advancements in photolithography techniques.

Recent papers by Sung Kyu Lim highlight developments in chip design and electronic device technologies. These include:

  • "Architecture, Chip, and Package Codesign Flow for Interposer-Based 2.5-D Chiplet Integration Enabling Heterogeneous IP Reuse" (2020), published in IEEE Transactions on Very Large Scale Integration (VLSI) Systems
  • "Antiferroelectric negative capacitance from a structural phase transition in zirconia" (2022), published in Nature Communications
  • "Heterogeneous Mixed-Signal Monolithic 3-D In-Memory Computing Using Resistive RAM" (2020), published in IEEE Transactions on Very Large Scale Integration (VLSI) Systems
  • "Chiplet/Interposer Co-Design for Power Delivery Network Optimization in Heterogeneous 2.5-D ICs" (2021), published in IEEE Transactions on Components Packaging and Manufacturing Technology
  • "Performance, Power, and Area of Standard Cells in Sub 3 nm Node Using Buried Power Rail" (2022), published in IEEE Transactions on Electron Devices

Sung Kyu Lim has frequently collaborated with several researchers, notably Jinwoo Kim, Gauthaman Murali, Anthony Agnesina, Sai Pentapati, and Yi-Chen Lu, reflecting ongoing partnerships in their research activities.

The primary publication venues where Sung Kyu Lim has contributed extensively include:

  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems
  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
  • ACM Transactions on Design Automation of Electronic Systems
  • arXiv (Cornell University)
  • IEEE Transactions on Components Packaging and Manufacturing Technology

Best Publications

  • TSV stress-aware full-chip mechanical reliability analysis and optimization for 3D IC

    Moongon Jung;Joydeep Mitra;David Z. Pan;Sung Kyu Lim

  • Study of Through-Silicon-Via Impact on the 3-D Stacked IC Layout

    Dae Hyun Kim;K. Athikulwongse;Sung Kyu Lim

  • A study of Through-Silicon-Via impact on the 3D stacked IC layout

    Dae Hyun Kim;Krit Athikulwongse;Sung Kyu Lim

  • 3D-MAPS: 3D Massively parallel processor with stacked memory

    Dae Hyun Kim;Krit Athikulwongse;Michael Healy;Mohammad Hossain

  • TSV stress aware timing analysis with applications to 3D-IC layout optimization

    Jae-Seok Yang;Krit Athikulwongse;Young-Joon Lee;Sung Kyu Lim

  • Thermal Characterization of Interlayer Microfluidic Cooling of Three-Dimensional Integrated Circuits With Nonuniform Heat Flux

    Yoon Jo Kim;Yogendra K. Joshi;Andrei G. Fedorov;Young-Joon Lee

  • Design and CAD methodologies for low power gate-level monolithic 3D ICs

    Shreepad A. Panth;Kambiz Samadi;Yang Du;Sung Kyu Lim

  • Multiobjective Microarchitectural Floorplanning for 2-D and 3-D ICs

    M. Healy;M. Vittes;M. Ekpanyapong;C.S. Ballapuram

  • 3D Floorplanning with Thermal Vias

    Eric Wong;Sung Kyu Lim

  • Physical design for 3D system on package

    S.K. Lim

  • Stress-driven 3D-IC placement with TSV keep-out zone and regularity study

    Krit Athikulwongse;Ashutosh Chakraborty;Jae-Seok Yang;David Z. Pan

  • Edge separability-based circuit clustering with application to multilevel circuit partitioning

    J. Cong;Sung Kyu Lim

  • Full-chip TSV-to-TSV coupling analysis and optimization in 3D IC

    Chang Liu;Taigon Song;Jonghyun Cho;Joohee Kim

  • A design tradeoff study with monolithic 3D integration

    Chang Liu;Sung Kyu Lim

  • Placement-Driven Partitioning for Congestion Mitigation in Monolithic 3D IC Designs

    Shreepad Panth;Kambiz Samadi;Yang Du;Sung Kyu Lim

  • Fast and Accurate Analytical Modeling of Through-Silicon-Via Capacitive Coupling

    Dae Hyun Kim;S Mukhopadhyay;Sung Kyu Lim

  • Multiway partitioning with pairwise movement

    Jason Cong;Sung Kyu Lim

  • Design and analysis of 3D-MAPS: A many-core 3D processor with stacked memory

    Michael B. Healy;Krit Athikulwongse;Rohan Goel;Mohammad M. Hossain

  • Physical planning with retiming

    Jason Cong;Sung Kyu Lim

  • Low-Power and Reliable Clock Network Design for Through-Silicon Via (TSV) Based 3D ICs

    Xin Zhao;J Minz;Sung Kyu Lim

  • Thermal Characterization of Interlayer Microfluidic Cooling of Three-Dimensional Integrated Circuits With Nonuniform Heat

    Yoon Jo Kim;Yogendra K. Joshi;Andrei G. Fedorov;Young-Joon Lee

Frequent Co-Authors

Saibal Mukhopadhyay
Saibal Mukhopadhyay Georgia Institute of Technology
David Z. Pan
David Z. Pan The University of Texas at Austin
Krishnendu Chakrabarty
Krishnendu Chakrabarty Arizona State University
Madhavan Swaminathan
Madhavan Swaminathan Pennsylvania State University
Michael Niemier
Michael Niemier University of Notre Dame
Joungho Kim
Joungho Kim Korea Advanced Institute of Science and Technology
Garrett S. Rose
Garrett S. Rose University of Tennessee at Knoxville
Asif Islam Khan
Asif Islam Khan Georgia Institute of Technology
Yu Cao
Yu Cao University of Minnesota
Paul Hasler
Paul Hasler Georgia Institute of Technology

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