H-Index & Metrics Best Publications

H-Index & Metrics

Discipline name H-index Citations Publications World Ranking National Ranking
Computer Science D-index 40 Citations 6,256 212 World Ranking 4408 National Ranking 2201
Electronics and Electrical Engineering D-index 41 Citations 6,905 262 World Ranking 1728 National Ranking 753

Research.com Recognitions

Awards & Achievements

2017 - SPIE Fellow

Overview

What is he best known for?

The fields of study he is best known for:

  • Artificial intelligence
  • Electrical engineering
  • Integrated circuit

Electronic engineering, Lithography, Routing, Integer programming and Very-large-scale integration are his primary areas of study. His Electronic engineering research is multidisciplinary, relying on both Stress, Interconnection and Standard cell. His Lithography study incorporates themes from Physical design, Node and Artificial intelligence.

The concepts of his Routing study are interwoven with issues in Key, Design closure, Design for manufacturability and Router. His Integer programming research is multidisciplinary, incorporating elements of Linear programming and Speedup, Parallel computing. David Z. Pan works mostly in the field of Very-large-scale integration, limiting it down to concerns involving Integrated circuit layout and, occasionally, Floorplan and Algorithm design.

His most cited work include:

  • AppSAT: Approximately deobfuscating integrated circuits (161 citations)
  • Redundant-via enhanced maze routing for yield improvement (157 citations)
  • Buffer block planning for interconnect-driven floorplanning (147 citations)

What are the main themes of his work throughout his whole career to date?

David Z. Pan mainly investigates Electronic engineering, Lithography, Very-large-scale integration, Routing and Algorithm. The study incorporates disciplines such as Photonics and Chip in addition to Electronic engineering. The various areas that David Z. Pan examines in his Lithography study include Computer engineering, Extreme ultraviolet lithography, Multiple patterning, Node and Design for manufacturability.

David Z. Pan has researched Very-large-scale integration in several fields, including Key, Design closure and Parallel computing. His work deals with themes such as Benchmark and Router, which intersect with Routing. David Z. Pan does research in Algorithm, focusing on Integer programming specifically.

He most often published in these fields:

  • Electronic engineering (30.12%)
  • Lithography (18.88%)
  • Very-large-scale integration (14.26%)

What were the highlights of his more recent work (between 2019-2021)?

  • Artificial neural network (5.02%)
  • Computer engineering (9.84%)
  • Artificial intelligence (6.83%)

In recent papers he was focusing on the following fields of study:

The scientist’s investigation covers issues in Artificial neural network, Computer engineering, Artificial intelligence, Electronic engineering and Very-large-scale integration. His work carried out in the field of Computer engineering brings together such families of science as Logic gate, Key, Leverage and Integrated circuit. His research integrates issues of Machine learning and Pattern recognition in his study of Artificial intelligence.

David Z. Pan is studying Noise shaping, which is a component of Electronic engineering. His Very-large-scale integration research is multidisciplinary, incorporating perspectives in Design flow, Design closure, Semiconductor device fabrication, Design for manufacturability and Engineering design process. His Deep learning study combines topics from a wide range of disciplines, such as Algorithm, Bar and Lithography.

Between 2019 and 2021, his most popular works were:

  • Electronic-photonic arithmetic logic unit for high-speed computing. (19 citations)
  • 9.5 A 13.5b-ENOB Second-Order Noise-Shaping SAR with PVT-Robust Closed-Loop Dynamic Amplifier (9 citations)
  • Towards Area-Efficient Optical Neural Networks: An FFT-based Architecture (8 citations)

In his most recent research, the most cited papers focused on:

  • Artificial intelligence
  • Electrical engineering
  • Integrated circuit

David Z. Pan mainly focuses on Computer engineering, Artificial neural network, Electronic circuit, Speedup and Design flow. His Artificial neural network research integrates issues from Algorithm, Fast Fourier transform, Deep learning and Inference. His Design flow research includes elements of Multiple patterning, Very-large-scale integration, Design closure and Open source.

His Leverage study deals with Integrated circuit intersecting with Lithography. His Arithmetic logic unit research includes themes of Electronic engineering and Electrical efficiency. The Electronic engineering study combines topics in areas such as Clock rate, Transistor and Wavelength-division multiplexing.

This overview was generated by a machine learning system which analysed the scientist’s body of work. If you have any feedback, you can contact us here.

Best Publications

Layout decomposition for triple patterning lithography

Bei Yu;Kun Yuan;Boyang Zhang;Duo Ding.
international conference on computer aided design (2011)

246 Citations

TSV stress-aware full-chip mechanical reliability analysis and optimization for 3D IC

Moongon Jung;Joydeep Mitra;David Z. Pan;Sung Kyu Lim.
Communications of The ACM (2014)

208 Citations

Pushing ASIC performance in a power envelope

Ruchir Puri;Leon Stok;John Cohn;David Kung.
design automation conference (2003)

205 Citations

AppSAT: Approximately deobfuscating integrated circuits

Kaveh Shamsi;Meng Li;Travis Meade;Zheng Zhao.
hardware oriented security and trust (2017)

196 Citations

CELONCEL: effective design technique for 3-D monolithic integration targeting high performance integrated circuits

Shashikanth Bobba;Ashutosh Chakraborty;Olivier Thomas;Perrine Batude.
asia and south pacific design automation conference (2011)

194 Citations

Redundant-via enhanced maze routing for yield improvement

Gang Xu;Li-Da Huang;David Z. Pan;Martin D. F. Wong.
asia and south pacific design automation conference (2005)

191 Citations

Buffer block planning for interconnect-driven floorplanning

Jason Cong;Tianming Kong;David Zhigang Pan.
international conference on computer aided design (1999)

186 Citations

Improved crosstalk modeling for noise constrained interconnect optimization

Jason Cong;David Zhigang Pan;Prasanna V. Srinivas.
asia and south pacific design automation conference (2001)

185 Citations

Layout Decomposition for Triple Patterning Lithography

Bei Yu;Kun Yuan;Duo Ding;David Z. Pan.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (2015)

173 Citations

Double Patterning Layout Decomposition for Simultaneous Conflict and Stitch Minimization

Kun Yuan;Jae-Seok Yang;D.Z. Pan.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (2010)

151 Citations

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