2017 - SPIE Fellow
Electronic engineering, Lithography, Routing, Integer programming and Very-large-scale integration are his primary areas of study. His Electronic engineering research is multidisciplinary, relying on both Stress, Interconnection and Standard cell. His Lithography study incorporates themes from Physical design, Node and Artificial intelligence.
The concepts of his Routing study are interwoven with issues in Key, Design closure, Design for manufacturability and Router. His Integer programming research is multidisciplinary, incorporating elements of Linear programming and Speedup, Parallel computing. David Z. Pan works mostly in the field of Very-large-scale integration, limiting it down to concerns involving Integrated circuit layout and, occasionally, Floorplan and Algorithm design.
David Z. Pan mainly investigates Electronic engineering, Lithography, Very-large-scale integration, Routing and Algorithm. The study incorporates disciplines such as Photonics and Chip in addition to Electronic engineering. The various areas that David Z. Pan examines in his Lithography study include Computer engineering, Extreme ultraviolet lithography, Multiple patterning, Node and Design for manufacturability.
David Z. Pan has researched Very-large-scale integration in several fields, including Key, Design closure and Parallel computing. His work deals with themes such as Benchmark and Router, which intersect with Routing. David Z. Pan does research in Algorithm, focusing on Integer programming specifically.
The scientist’s investigation covers issues in Artificial neural network, Computer engineering, Artificial intelligence, Electronic engineering and Very-large-scale integration. His work carried out in the field of Computer engineering brings together such families of science as Logic gate, Key, Leverage and Integrated circuit. His research integrates issues of Machine learning and Pattern recognition in his study of Artificial intelligence.
David Z. Pan is studying Noise shaping, which is a component of Electronic engineering. His Very-large-scale integration research is multidisciplinary, incorporating perspectives in Design flow, Design closure, Semiconductor device fabrication, Design for manufacturability and Engineering design process. His Deep learning study combines topics from a wide range of disciplines, such as Algorithm, Bar and Lithography.
David Z. Pan mainly focuses on Computer engineering, Artificial neural network, Electronic circuit, Speedup and Design flow. His Artificial neural network research integrates issues from Algorithm, Fast Fourier transform, Deep learning and Inference. His Design flow research includes elements of Multiple patterning, Very-large-scale integration, Design closure and Open source.
His Leverage study deals with Integrated circuit intersecting with Lithography. His Arithmetic logic unit research includes themes of Electronic engineering and Electrical efficiency. The Electronic engineering study combines topics in areas such as Clock rate, Transistor and Wavelength-division multiplexing.
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Layout decomposition for triple patterning lithography
Bei Yu;Kun Yuan;Boyang Zhang;Duo Ding.
international conference on computer aided design (2011)
TSV stress-aware full-chip mechanical reliability analysis and optimization for 3D IC
Moongon Jung;Joydeep Mitra;David Z. Pan;Sung Kyu Lim.
Communications of The ACM (2014)
Pushing ASIC performance in a power envelope
Ruchir Puri;Leon Stok;John Cohn;David Kung.
design automation conference (2003)
AppSAT: Approximately deobfuscating integrated circuits
Kaveh Shamsi;Meng Li;Travis Meade;Zheng Zhao.
hardware oriented security and trust (2017)
CELONCEL: effective design technique for 3-D monolithic integration targeting high performance integrated circuits
Shashikanth Bobba;Ashutosh Chakraborty;Olivier Thomas;Perrine Batude.
asia and south pacific design automation conference (2011)
Redundant-via enhanced maze routing for yield improvement
Gang Xu;Li-Da Huang;David Z. Pan;Martin D. F. Wong.
asia and south pacific design automation conference (2005)
Buffer block planning for interconnect-driven floorplanning
Jason Cong;Tianming Kong;David Zhigang Pan.
international conference on computer aided design (1999)
Improved crosstalk modeling for noise constrained interconnect optimization
Jason Cong;David Zhigang Pan;Prasanna V. Srinivas.
asia and south pacific design automation conference (2001)
Layout Decomposition for Triple Patterning Lithography
Bei Yu;Kun Yuan;Duo Ding;David Z. Pan.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (2015)
Double Patterning Layout Decomposition for Simultaneous Conflict and Stitch Minimization
Kun Yuan;Jae-Seok Yang;D.Z. Pan.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (2010)
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