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Computer Science

D-Index
71
Citations
17703
World Ranking
1792
National Ranking
905

Electronics and Electrical Engineering

D-Index
70
Citations
17459
World Ranking
930
National Ranking
390

Research.com Recognitions

  • 2017 - SPIE Fellow

Overview

David Z. Pan is affiliated with The University of Texas at Austin in the United States. Their research spans multiple intersecting domains primarily within engineering and computer science.

The main fields of study for their work include:

  • Engineering
  • Computer Science

Within these broad areas, their subfields of study cover:

  • Electrical and Electronic Engineering
  • Artificial Intelligence
  • Hardware and Architecture
  • Computer Vision and Pattern Recognition
  • Biomedical Engineering

Research topics frequently addressed by David Z. Pan involve:

  • Neural Networks and Reservoir Computing
  • Optical Network Technologies
  • Photonic and Optical Devices
  • VLSI and FPGA Design Techniques
  • Advancements in Photolithography Techniques
  • Advancements in Semiconductor Devices and Circuit Design
  • VLSI and Analog Circuit Testing

Their recent scholarly contributions include papers such as:

  • "An Energy-Efficient Comparator With Dynamic Floating Inverter Amplifier," 2020, IEEE Journal of Solid-State Circuits
  • "Multi-Scale High-Resolution Vision Transformer for Semantic Segmentation," 2022, 2022 IEEE/CVF Conference on Computer Vision and Pattern Recognition (CVPR)
  • "Electronic-photonic arithmetic logic unit for high-speed computing," 2020, Nature Communications
  • "DREAMPlace: Deep Learning Toolkit-Enabled GPU Acceleration for Modern VLSI Placement," 2020, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
  • "A 13.5-ENOB, 107-μW Noise-Shaping SAR ADC With PVT-Robust Closed-Loop Dynamic Amplifier," 2020, IEEE Journal of Solid-State Circuits

Frequent coauthors in this research include:

  • Jiaqi Gu
  • Ray T. Chen
  • Zixuan Jiang
  • Keren Zhu
  • Hanqing Zhu

The venues where David Z. Pan has been regularly published consist of:

  • arXiv (Cornell University)
  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
  • IEEE Journal of Solid-State Circuits
  • 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC)
  • Conference on Lasers and Electro-Optics

David Z. Pan was recognized as an SPIE Fellow in 2017.

Best Publications

  • TSV stress-aware full-chip mechanical reliability analysis and optimization for 3D IC

    Moongon Jung;Joydeep Mitra;David Z. Pan;Sung Kyu Lim

  • AppSAT: Approximately deobfuscating integrated circuits

    Kaveh Shamsi;Meng Li;Travis Meade;Zheng Zhao

  • Multi-Scale High-Resolution Vision Transformer for Semantic Segmentation

    Unknown

  • Provably Secure Camouflaging Strategy for IC Protection

    Meng Li;Kaveh Shamsi;Travis Meade;Zheng Zhao

  • BoxRouter: A New Global Router Based on Box Expansion and Progressive ILP

    Minsik Cho;D.Z. Pan

  • Double Patterning Layout Decomposition for Simultaneous Conflict and Stitch Minimization

    Kun Yuan;Jae-Seok Yang;D.Z. Pan

  • Interconnect design for deep submicron ICs

    Jason Cong;Zhigang Pan;Lei He;Cheng-Kok Koh

  • An Energy-Efficient Comparator With Dynamic Floating Inverter Amplifier

    Xiyuan Tang;Linxiao Shen;Begum Kasap;Xiangxing Yang

  • CELONCEL: effective design technique for 3-D monolithic integration targeting high performance integrated circuits

    Shashikanth Bobba;Ashutosh Chakraborty;Olivier Thomas;Perrine Batude

  • Pushing ASIC performance in a power envelope

    Ruchir Puri;Leon Stok;John Cohn;David Kung

  • Improved crosstalk modeling for noise constrained interconnect optimization

    Jason Cong;David Zhigang Pan;Prasanna V. Srinivas

  • Buffer block planning for interconnect-driven floorplanning

    Jason Cong;Tianming Kong;David Zhigang Pan

  • Redundant-via enhanced maze routing for yield improvement

    Gang Xu;Li-Da Huang;David Z. Pan;Martin D. F. Wong

  • Layout Decomposition for Triple Patterning Lithography

    Bei Yu;Kun Yuan;Duo Ding;David Z. Pan

  • A3MAP: Architecture-aware analytic mapping for networks-on-chip

    Wooyoung Jang;David Z. Pan

  • Cyclic Obfuscation for Creating SAT-Unresolvable Circuits

    Kaveh Shamsi;Meng Li;Travis Meade;Zheng Zhao

  • A High-Performance Droplet Routing Algorithm for Digital Microfluidic Biochips

    Minsik Cho;D.Z. Pan

  • DREAMPlace: Deep Learning Toolkit-Enabled GPU Acceleration for Modern VLSI Placement

    Yibo Lin;Zixuan Jiang;Jiaqi Gu;Wuxi Li

  • Self-Aligned Double Patterning Aware Pin Access and Standard Cell Layout Co-Optimization

    Xiaoqing Xu;Brian Cline;Greg Yeric;Bei Yu

  • Layout decomposition for triple patterning lithography

    Bei Yu;Kun Yuan;Boyang Zhang;Duo Ding

  • TSV stress aware timing analysis with applications to 3D-IC layout optimization

    Jae-Seok Yang;Krit Athikulwongse;Young-Joon Lee;Sung Kyu Lim

  • RADAR: RET-aware detailed routing using fast lithography simulations

    Joydeep Mitra;Peng Yu;David Z. Pan

Frequent Co-Authors

Bei Yu
Bei Yu Chinese University of Hong Kong
Nan Sun
Nan Sun Tsinghua University
Sung Kyu Lim
Sung Kyu Lim Georgia Institute of Technology
Yier Jin
Yier Jin University of Florida
Charles J. Alpert
Charles J. Alpert Cadence Design Systems
Richard A. Soref
Richard A. Soref University of Massachusetts Boston
Päivi Pajukanta
Päivi Pajukanta University of California, Los Angeles
Michael Orshansky
Michael Orshansky The University of Texas at Austin
Jason Cong
Jason Cong University of California, Los Angeles
Ru Huang
Ru Huang Peking University

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