His primary areas of study are Algorithm, Mathematical optimization, Very-large-scale integration, Routing and Steiner tree problem. His Algorithm study combines topics in areas such as Circuit design and Cluster analysis. His study in the fields of Quadratic programming, Solver and Iterative method under the domain of Mathematical optimization overlaps with other disciplines such as Scalability.
His work carried out in the field of Very-large-scale integration brings together such families of science as Integrated circuit layout, Floorplan and Parallel computing. Routing and Interconnection are commonly linked in his work. The Steiner tree problem study combines topics in areas such as Minimum spanning tree and Router.
His primary scientific interests are in Algorithm, Mathematical optimization, Routing, Floorplan and Very-large-scale integration. Much of his study explores Algorithm relationship to Integrated circuit layout. His work in Mathematical optimization addresses issues such as Time complexity, which are connected to fields such as Minification.
His Routing research incorporates themes from Placement, Steiner tree problem and Router. His Floorplan research includes elements of Simulated annealing, Physical design, Representation and Interconnection. He usually deals with Very-large-scale integration and limits it to topics linked to Parallel computing and Netlist, Electronic design automation and Integrated circuit design.
His primary areas of investigation include Mathematical optimization, Algorithm, Parallel computing, Speedup and Electronic engineering. Specifically, his work in Mathematical optimization is concerned with the study of Heuristic. His Algorithm research is multidisciplinary, incorporating perspectives in Distributed algorithm and Dimensionality reduction.
His Parallel computing study integrates concerns from other disciplines, such as Dynamic programming, Floorplan, Function, Block and Flexibility. He has included themes like Pixel, Lagrangian relaxation and Logic gate in his Speedup study. His Routing study in the realm of Electronic engineering connects with subjects such as Threshold voltage.
Chris Chu mainly investigates Routing, Parallel computing, Algorithm, Speedup and Overlay. His Routing study combines topics from a wide range of disciplines, such as Function, Node, Dynamic programming and Design for manufacturability. His Design for manufacturability research focuses on subjects like Reliability, which are linked to Heuristic.
The various areas that he examines in his Parallel computing study include Computer hardware, Netlist, Tree traversal, Lagrangian relaxation and Flexibility. The concepts of his Algorithm study are interwoven with issues in Very-large-scale integration, Asynchronous communication, Standard cell and Robustness. His work deals with themes such as Logic gate and Mutual exclusion, which intersect with Speedup.
This overview was generated by a machine learning system which analysed the scientist’s body of work. If you have any feedback, you can contact us here.
Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation
Chung-Ping Chen;Chris C. N. Chu;D. F. Wong.
international conference on computer aided design (1998)
FastPlace: efficient analytical placement using cell shifting, iterative local refinement,and a hybrid net model
N. Viswanathan;C.C.-N. Chu.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (2005)
A matrix synthesis approach to thermal placement
C.C.N. Chu;D.F. Wong.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (1998)
FLUTE: Fast Lookup Table Based Rectilinear Steiner Minimal Tree Algorithm for VLSI Design
C. Chu;Yiu-Chung Wong.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (2008)
An efficient and effective detailed placement algorithm
Min Pan;N. Viswanathan;C. Chu.
international conference on computer aided design (2005)
FastPlace 3.0: A Fast Multilevel Quadratic Placement Algorithm with Placement Congestion Control
N. Viswanathan;Min Pan;C. Chu.
asia and south pacific design automation conference (2007)
FastRoute 4.0: global router with efficient via minimization
Yue Xu;Yanheng Zhang;Chris Chu.
asia and south pacific design automation conference (2009)
FLUTE: fast lookup table based wirelength estimation technique
C. Chu.
international conference on computer aided design (2004)
FastRoute: a step to integrate global routing into placement
Min Pan;Chris Chu.
international conference on computer aided design (2006)
FastRoute 2.0: A High-quality and Efficient Global Router
Min Pan;C. Chu.
asia and south pacific design automation conference (2007)
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