1999 - IEEE Fellow For contributions to the area of test generation for digital logic circuits.
Algorithm, Automatic test pattern generation, Fault coverage, Sequential logic and Fault are her primary areas of study. The concepts of her Algorithm study are interwoven with issues in Test set and Fault detection and isolation. Her Automatic test pattern generation research is multidisciplinary, incorporating perspectives in Electronic engineering, Benchmark and Stuck-at fault.
In Fault coverage, Irith Pomeranz works on issues like Reliability engineering, which are connected to Measure, Automatic test equipment and Structural engineering. The various areas that she examines in her Sequential logic study include State, Synchronization, Test strategy, Simulation and Sequence. Irith Pomeranz interconnects Computation and Resolution in the investigation of issues within Fault.
Irith Pomeranz mainly investigates Algorithm, Fault coverage, Automatic test pattern generation, Fault and Test set. Her Algorithm study combines topics from a wide range of disciplines, such as Test, Electronic circuit, Benchmark and Fault detection and isolation. Her research in Electronic circuit intersects with topics in Electronic engineering and Logic gate.
Her work in Fault coverage tackles topics such as Stuck-at fault which are related to areas like Fault indicator and Fault model. In her study, Boundary scan is strongly linked to Scan chain, which falls under the umbrella field of Automatic test pattern generation. The study incorporates disciplines such as Very-large-scale integration and Computation in addition to Test set.
Her scientific interests lie mostly in Algorithm, Benchmark, Test set, Electronic circuit and Fault coverage. Her Algorithm study combines topics from a wide range of disciplines, such as Fault, Sequence, Very-large-scale integration and Volume. Her Test set research is multidisciplinary, incorporating elements of Test, Compaction, Fault detection and isolation, Scan chain and Computation.
In her study, which falls under the umbrella issue of Electronic circuit, Mode is strongly linked to Electronic engineering. Irith Pomeranz has included themes like Computational complexity theory, Automatic test pattern generation and Test sequence in her Fault coverage study. Her work in Automatic test pattern generation addresses issues such as Stuck-at fault, which are connected to fields such as Fault indicator.
Her main research concerns Algorithm, Benchmark, Fault, Test set and Fault coverage. Her Algorithm research integrates issues from Test compression and Very-large-scale integration. Irith Pomeranz has researched Fault in several fields, including Sequential logic and Flexibility.
The various areas that she examines in her Test set study include Test and Data collection. Her Fault coverage research is multidisciplinary, relying on both Computational complexity theory, Cube and Automatic test pattern generation. Her research integrates issues of Reliability engineering and Stuck-at fault in her study of Automatic test pattern generation.
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COMPACTEST: a method to generate compact test sets for combinational circuits
I. Pomeranz;L.N. Reddy;S.M. Reddy.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (1993)
Transient-fault recovery for chip multiprocessors
Mohamed Gomaa;Chad Scarbrough;T. N. Vijaykumar;Irith Pomeranz.
international symposium on computer architecture (2003)
Transient-fault recovery using simultaneous multithreading
T. N. Vijaykumar;Irith Pomeranz;Karl Cheng.
international symposium on computer architecture (2002)
Cost-effective generation of minimal test sets for stuck-at faults in combinational logic circuits
S. Kajihara;I. Pomeranz;K. Kinoshita;S.M. Reddy.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (1995)
Techniques for minimizing power dissipation in scan and combinational circuits during test application
V. Dabholkar;S. Chakravarty;I. Pomeranz;S. Reddy.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (1998)
Preferred Fill: A Scalable Method to Reduce Capture Power for Scan Based Designs
Santiago Remersaro;Xijiang Lin;Zhuo Zhang;Sudhakar Reddy.
international test conference (2006)
On test data volume reduction for multiple scan chain designs
Sudhakar M. Reddy;Kohei Miyase;Seiji Kajihara;Irith Pomeranz.
ACM Transactions on Design Automation of Electronic Systems (2003)
On n-detection test sets and variable n-detection test sets for transition faults
I. Pomeranz;S.M. Reddy.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (2000)
3-weight pseudo-random test generation based on a deterministic test set for combinational and sequential circuits
I. Pomeranz;S.M. Reddy.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (1993)
A Low Power Pseudo-Random BIST Technique
Nadir Z. Basturkmen;Sudhakar M. Reddy;Irith Pomeranz.
Journal of Electronic Testing (2003)
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