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Computer Science

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Electronics and Electrical Engineering

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1964
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Research.com Recognitions

  • 1999 - IEEE Fellow For contributions to the area of test generation for digital logic circuits.

Overview

Irith Pomeranz is affiliated with Purdue University West Lafayette in the United States. Their research primarily focuses on engineering and computer science, with a specialization in electrical and electronic engineering and hardware architecture. Their work covers extensive aspects of VLSI and analog circuit testing, integrated circuits and semiconductor failure analysis, and radiation effects in electronics.

Their body of published work includes contributions to multiple fields and subfields such as low-power high-performance VLSI design, VLSI and FPGA design techniques, software testing and debugging techniques, advancements in photolithography techniques, control and systems engineering, and computer networks and communications.

Notable recent papers include:

  • "Maximal Independent Fault Set for Gate-Exhaustive Faults" (2020), IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
  • "Storage-Based Built-In Self-Test for Gate-Exhaustive Faults" (2020), IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
  • "Functional Constraints in the Selection of Two-Cycle Gate-Exhaustive Faults for Test Generation" (2021), IEEE Transactions on Very Large Scale Integration (VLSI) Systems
  • "Hybrid Pass/Fail and Full Fail Data for Reduced Fail Data Volume" (2020), IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
  • "In-Field Testing of Functionally-Possible Transition Faults With High Activation Frequencies" (2024), IEEE Transactions on Device and Materials Reliability

Frequent co-authors in their research work include:

  • Y. Zorian
  • M. Enamul Amyeen
  • Hari Addepalli
  • Srikanth Venkataraman
  • Xijiang Lin

Pomeranz's publications commonly appear in venues such as:

  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems
  • ACM Transactions on Design Automation of Electronic Systems
  • IEEE Access
  • Proceedings of the Great Lakes Symposium on VLSI 2022

The scope of their research topics encompasses:

  • VLSI and Analog Circuit Testing
  • Integrated Circuits and Semiconductor Failure Analysis
  • Radiation Effects in Electronics
  • Low-power high-performance VLSI design
  • VLSI and FPGA Design Techniques
  • Software Testing and Debugging Techniques
  • Advancements in Photolithography Techniques

In recognition of their contributions to digital logic circuit testing, Irith Pomeranz was named an IEEE Fellow in 1999.

Best Publications

  • COMPACTEST: a method to generate compact test sets for combinational circuits

    I. Pomeranz;L.N. Reddy;S.M. Reddy

  • Transient-fault recovery for chip multiprocessors

    Mohamed Gomaa;Chad Scarbrough;T. N. Vijaykumar;Irith Pomeranz

  • Transient-fault recovery using simultaneous multithreading

    T. N. Vijaykumar;Irith Pomeranz;Karl Cheng

  • Cost-effective generation of minimal test sets for stuck-at faults in combinational logic circuits

    S. Kajihara;I. Pomeranz;K. Kinoshita;S.M. Reddy

  • Techniques for minimizing power dissipation in scan and combinational circuits during test application

    V. Dabholkar;S. Chakravarty;I. Pomeranz;S. Reddy

  • Preferred Fill: A Scalable Method to Reduce Capture Power for Scan Based Designs

    Santiago Remersaro;Xijiang Lin;Zhuo Zhang;Sudhakar Reddy

  • On test data volume reduction for multiple scan chain designs

    Sudhakar M. Reddy;Kohei Miyase;Seiji Kajihara;Irith Pomeranz

  • On n-detection test sets and variable n-detection test sets for transition faults

    I. Pomeranz;S.M. Reddy

  • 3-weight pseudo-random test generation based on a deterministic test set for combinational and sequential circuits

    I. Pomeranz;S.M. Reddy

  • A Low Power Pseudo-Random BIST Technique

    Nadir Z. Basturkmen;Sudhakar M. Reddy;Irith Pomeranz

  • On static compaction of test sequences for synchronous sequential circuits

    Irith Pomeranz;Sudhakar M. Reddy

  • Vector restoration based static compaction of test sequences for synchronous sequential circuits

    I. Pomeranz;S.M. Reddy

  • Fault dictionary compression and equivalence class computation for sequential circuits

    Paul G. Ryan;W. Kent Fuchs;Irith Pomeranz

  • LOCSTEP: a logic-simulation-based test generation procedure

    I. Pomeranz;S.M. Reddy

  • Classification of faults in synchronous sequential circuits

    I. Pomeranz;S.M. Reddy

  • On the generation of scan-based test sets with reachable states for testing under functional operation conditions

    Irith Pomeranz

  • On reducing peak current and power during test

    Wei Li;S.M. Reddy;I. Pomeranz

  • Generation of Functional Broadside Tests for Transition Faults

    I. Pomeranz;S.M. Reddy

  • On-chip compression of output responses with unknown values using lfsr reseeding

    M. Naruse;I. Porneranz;S.M. Reddy;S. Kundu

  • NEST: a nonenumerative test generation method for path delay faults in combinational circuits

    I. Pomeranz;S.M. Reddy;P. Uppaluri

  • 3-Weight Pseudo-Random Test Generation Based on a Deterministic Test Set

    I. Pomeranz;S.M. Reddy

Frequent Co-Authors

Sudhakar M. Reddy
Sudhakar M. Reddy University of Iowa
Janusz Rajski
Janusz Rajski Siemens (Germany)
Bernd Becker
Bernd Becker University of Freiburg
Seiji Kajihara
Seiji Kajihara Kyushu Institute of Technology
Sandip Kundu
Sandip Kundu University of Massachusetts Amherst
W.K. Fuchs
W.K. Fuchs University of Florida
T. N. Vijaykumar
T. N. Vijaykumar Purdue University West Lafayette
Ilia Polian
Ilia Polian University of Stuttgart
Jerzy Tyszer
Jerzy Tyszer Poznań University of Technology
Kwang-Ting Cheng
Kwang-Ting Cheng Hong Kong University of Science and Technology

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