World's Best Scientists 2026 revealed!

D-Index & Metrics

Engineering and Technology

D-Index
44
Citations
6689
World Ranking
5879
National Ranking
105

Overview

Xiaoqing Wen is affiliated with the Kyushu Institute of Technology in Japan and has contributed extensively to research in engineering and computer science. Their publication record spans several subfields including electrical and electronic engineering, hardware and architecture, computer networks and communications, computational theory and mathematics, and molecular biology.

Their research primarily focuses on topics related to radiation effects in electronics, VLSI and analog circuit testing, semiconductor materials and devices, integrated circuits and semiconductor failure analysis, low-power high-performance VLSI design, advancements in semiconductor devices and circuit design, and physical unclonable functions (PUFs) and hardware security.

Wen has authored or co-authored numerous papers with frequent collaborators including Aibin Yan, Zhengfeng Huang, Tianming Ni, Patrick Girard, and Jie Cui.

They have published in a variety of reputable outlets, with frequent publications in:

  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems (14 publications)
  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (13 publications)
  • IEEE Transactions on Aerospace and Electronic Systems (8 publications)
  • Microelectronics Journal (4 publications)
  • SSRN Electronic Journal (4 publications)

Representative papers include:

  • A Secure and Multiobjective Virtual Machine Placement Framework for Cloud Data Center, 2021, IEEE Systems Journal
  • Information Assurance Through Redundant Design: A Novel TNU Error-Resilient Latch for Harsh Radiation Environment, 2020, IEEE Transactions on Computers
  • Novel Quadruple-Node-Upset-Tolerant Latch Designs With Optimized Overhead for Reliable Computing in Harsh Radiation Environments, 2020, IEEE Transactions on Emerging Topics in Computing
  • Novel Speed-and-Power-Optimized SRAM Cell Designs With Enhanced Self-Recoverability From Single- and Double-Node Upsets, 2020, IEEE Transactions on Circuits and Systems I Regular Papers
  • Quadruple and Sextuple Cross-Coupled SRAM Cell Designs With Optimized Overhead for Reliable Applications, 2022, IEEE Transactions on Device and Materials Reliability

Best Publications

  • VLSI Test Principles and Architectures: Design for Testability

    Laung-Terng Wang;Cheng-Wen Wu;Xiaoqing Wen

  • VLSI Test Principles and Architectures

    Laung Terng Wang;Cheng Wen Wu;Xiaoqing Wen

  • On low-capture-power test generation for scan testing

    Xiaoqing Wen;Y. Yamashita;S. Kajihara;Laung-Terng Wang

  • Computer-aided design system to automate scan synthesis at register-transfer level

    Laung-Terng Wang;Xiaoqing Wen

  • Low-capture-power test generation for scan-based at-speed testing

    Xiaoqing Wen;Y. Yamashita;S. Morishima;S. Kajihara

  • VLSI Test Principles and Architectures: Design for Testability (Systems on Silicon)

    Laung-Terng Wang;Cheng-Wen Wu;Xiaoqing Wen

  • Method and apparatus for diagnosing failures in an integrated circuit using design-for-debug (dfd) techniques

    Laung-Terng (L.-T.) Wang;Ming-Tung Chang;Shyh-Horng Lin;Hao-Jan Chao

  • Power-Aware Testing and Test Strategies for Low Power Devices

    Dimitris Gizopoulos;Kaushik Roy;Patrick Girard;Nicola Nicolici

  • Design for Testability

    Laung-Terng (L.-T.) Wang;Xiaoqing Wen;Khader S. Abdel-Hafez

  • VirtualScan: a new compressed scan technology for test cost reduction

    L.-T. Wang;Xiaoqing Wen;H. Furukawa;Fei-Sheng Hsu

  • A new ATPG method for efficient capture power reduction during scan testing

    Xiaoqing Wen;S. Kajihara;K. Miyase;T. Suzuki

  • Multiple-capture dft system for detecting or locating crossing clock-domain faults during self-test or scan test

    Laung-Terng Wang;Po-Ching Hsu;Shih-Chia F No. Kao;Meng-Chyi Lin

  • Power-Aware Testing and Test Strategies for Low Power Devices

    Patrick Girard;Nicola Nicolici;Xiaoqing Wen

  • Method and apparatus for debug, diagnosis, and yield improvement of scan-based integrated circuits

    Khader S. Abdel-Hafez;Xiaoqing Wen;Laung-Terng Wang;Po-Ching Hsu

  • A novel scheme to reduce power supply noise for high-quality at-speed scan testing

    Xiaoqing Wen;K. Miyase;S. Kajihara;T. Suzuki

  • Mask network design for scan-based integrated circuits

    Laung-Terng L-T Wang;Khader S Abdel-Hafez;Xiaoqing Wen;Boryau Jack Sheu

  • Novel Low Cost, Double-and-Triple-Node-Upset-Tolerant Latch Designs for Nano-scale CMOS

    Aibin Yan;Chaoping Lai;Yinlei Zhang;Jie Cui

  • Quadruple and Sextuple Cross-Coupled SRAM Cell Designs With Optimized Overhead for Reliable Applications

    Unknown

  • Information Assurance Through Redundant Design: A Novel TNU Error-Resilient Latch for Harsh Radiation Environment

    Aibin Yan;Yuanjie Hu;Jie Cui;Zhili Chen

  • Mehrfacherfassungs-dft-system für integrierte schaltungen auf scan-basis

    Laung-Terng Wang;Shih-Chia Kao;Meng-Chyi Lin;Hsin-Po Wang

  • Design of a Triple-Node-Upset Self-Recoverable Latch for Aerospace Applications in Harsh Radiation Environments

    Aibin Yan;Xiangfeng Feng;Yuanjie Hu;Chaoping Lai

  • Critical-path-aware X-filling for effective IR-drop reduction in at-speed scan testing

    Xiaoqing Wen;Kohei Miyase;Tatsuya Suzuki;Seiji Kajihara

Frequent Co-Authors

Seiji Kajihara
Seiji Kajihara Kyushu Institute of Technology
Patrick Girard
Patrick Girard Montpellier Laboratory of Informatics, Robotics and Microelectronics
Kewal K. Saluja
Kewal K. Saluja University of Wisconsin–Madison
Jie Cui
Jie Cui University of Science and Technology of China
Mohammad Tehranipoor
Mohammad Tehranipoor University of Florida
Hans-Joachim Wunderlich
Hans-Joachim Wunderlich University of Stuttgart
Yu Hu
Yu Hu Institute Of Computing Technology
Nicola Nicolici
Nicola Nicolici McMaster University
Tsutomu Sasao
Tsutomu Sasao Meiji University
Bernd Becker
Bernd Becker University of Freiburg

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