His primary areas of study are Built-in self-test, Automatic test pattern generation, Fault coverage, Algorithm and Test compression. His Built-in self-test study incorporates themes from Overhead and Parallel computing. His study on Automatic test pattern generation is covered under Fault.
His Fault coverage research is multidisciplinary, incorporating elements of Design for testing, Sequential logic, Chip and Test strategy. His Algorithm research integrates issues from Electronic circuit, Fault detection and isolation, Self test, Function and Test set. His study in Test compression is interdisciplinary in nature, drawing from both Test data, Pseudorandom number generator and Scan chain.
His primary scientific interests are in Automatic test pattern generation, Fault coverage, Embedded system, Algorithm and Built-in self-test. His Automatic test pattern generation study combines topics in areas such as Design for testing, Electronic engineering and Benchmark. His Fault coverage study combines topics from a wide range of disciplines, such as Electronic circuit, Overhead, Reliability engineering and Stuck-at fault, Fault detection and isolation.
His studies in Embedded system integrate themes in fields like Fault tolerance, Redundancy and Debugging. Algorithm is often connected to Test set in his work. Hans-Joachim Wunderlich interconnects System testing, Real-time computing, Computer engineering and Parallel computing in the investigation of issues within Built-in self-test.
Hans-Joachim Wunderlich mostly deals with Embedded system, Fault, Fault tolerance, Reliability engineering and Electronic circuit. His Embedded system research is multidisciplinary, incorporating perspectives in Redundancy, Hardware security module, Debugging and Dependability. His is involved in several facets of Fault study, as is seen by his studies on Automatic test pattern generation and Fault coverage.
The Automatic test pattern generation study combines topics in areas such as Algorithm and Built-in self-test. His Fault tolerance research is multidisciplinary, relying on both Overhead, Reliability, Parallel computing, Conjugate gradient method and Error detection and correction. Hans-Joachim Wunderlich works mostly in the field of Electronic circuit, limiting it down to concerns involving CMOS and, occasionally, Logic level.
His primary areas of investigation include Embedded system, Reliability, Fault, Automatic test pattern generation and Fault tolerance. His work on Field-programmable gate array as part of general Embedded system study is frequently linked to Key, bridging the gap between disciplines. He has included themes like Electronic circuit and Logic gate in his Fault study.
His Automatic test pattern generation study integrates concerns from other disciplines, such as Built-in self-test, Fault coverage, Classification methods, Algorithm and Machine learning. His Algorithm research incorporates elements of Test compression and Test set. His work in Fault tolerance tackles topics such as Overhead which are related to areas like Parallel computing and Scalability.
This overview was generated by a machine learning system which analysed the scientist’s body of work. If you have any feedback, you can contact us here.
Minimized Power Consumption for Scan-Based BIST
Stefan Gerstendörfer;Hans-Joachim Wunderlich.
Journal of Electronic Testing (2000)
Multiple distributions for biased random test patterns
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (1990)
A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters
Sybille Hellebrand;Hua-Guo Liang;Hans-Joachim Wunderlich.
Journal of Electronic Testing (2001)
Hans-Joachim Wunderlich;Gundolf Kiefer.
international conference on computer aided design (1996)
Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST
Hua-Guo Liang;Sybille Hellebrand;Hans-Joachim Wunderlich.
Journal of Electronic Testing (2002)
Mixed-Mode BIST Using Embedded Processors
Sybille Hellebrand;Hans-Joachim Wunderlich;Andre Hertwig.
Journal of Electronic Testing (1998)
A modified clock scheme for a low power BIST test pattern generator
P. Girard;L. Guiller;C. Landrault;S. Pravossoudovitch.
vlsi test symposium (2001)
Pattern generation for a deterministic BIST scheme
Sybille Hellebrand;Birgit Reeb;Steffen Tarnick;Hans-Joachim Wunderlich.
international conference on computer aided design (1995)
PROTEST: A Tool for Probabilistic Testability Analysis
design automation conference (1985)
Adaptive Debug and Diagnosis without Fault Dictionaries
S. Hoist;H.-J. Wunderlich.
european test symposium (2007)
If you think any of the details on this page are incorrect, let us know.
We appreciate your kind effort to assist us to improve this page, it would be helpful providing us with as much detail as possible in the text box below: