2026 Seiji Kajihara: Computer Science Researcher – H-Index, Publications & Awards

Discipline name	D-Index	World Ranking	Current World Ranking	National Ranking	Current National Ranking	Publications	Citations
Computer Science	30	14077	13644	235	226	217	4015

Overview

Seiji Kajihara is affiliated with the Kyushu Institute of Technology in Japan. Their research activity primarily spans the fields of engineering and computer science, with notable contributions in electrical and electronic engineering, biomedical engineering, hardware and architecture, signal processing, and information systems.

Their published works focus on various specialized topics within integrated circuit technologies and related areas. Main topics include:

Advancements in PLL and VCO Technologies
Optical Network Technologies
Radio Frequency Integrated Circuit Design
Photonic and Optical Devices
Analog and Mixed-Signal Circuit Design
VLSI and Analog Circuit Testing
Integrated Circuits and Semiconductor Failure Analysis

Their recent papers demonstrate a focus on precise timing and signal processing in FPGA and integrated circuits. Selected publications are:

High-Precision PLL Delay Matrix With Overclocking and Double Data Rate for Accurate FPGA Time-to-Digital Converters, 2020, IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A 1-ps Bin Size 4.87-ps Resolution FPGA Time-to-Digital Converter Based on Phase Wrapping Sorting and Selection, 2022, IEEE Access
On the Efficacy of Scan Chain Grouping for Mitigating IR-Drop-Induced Test Data Corruption, 2021, IEICE Transactions on Information and Systems
Area Efficient 0.009-mm² 28.1-ppm/°C 11.3-MHz ALL-MOS Relaxation Oscillator, 2024, IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Frequent venues for publication include:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Access
IEICE Transactions on Information and Systems

Collaborative research is evident through several frequent coauthors, including:

Poki Chen
Tetsushi Ohki
Masakatsu Nishigaki
Ruei-Ting Wang
Y. Miyake

Seiji Kajihara's body of work contributes to the development and understanding of timing precision in FPGA technology, power integrity in integrated circuit testing, and oscillator design, among other areas related to advanced electronics and circuit systems.

Best Publications

Cost-effective generation of minimal test sets for stuck-at faults in combinational logic circuits

S. Kajihara;I. Pomeranz;K. Kinoshita;S.M. Reddy

390
Citations
On test data volume reduction for multiple scan chain designs

Sudhakar M. Reddy;Kohei Miyase;Seiji Kajihara;Irith Pomeranz

282
Citations
On low-capture-power test generation for scan testing

Xiaoqing Wen;Y. Yamashita;S. Kajihara;Laung-Terng Wang

230
Citations
Invisible delay quality - SDQM model lights up what could not be seen

Y. Sato;S. Hamada;T. Maeda;A. Takatori

176
Citations
Low-capture-power test generation for scan-based at-speed testing

Xiaoqing Wen;Y. Yamashita;S. Morishima;S. Kajihara

176
Citations
XID: Don't care identification of test patterns for combinational circuits

K. Miyase;S. Kajihara

141
Citations
Test vector modification for power reduction during scan testing

S. Kajihara;K. Ishida;K. Miyase

134
Citations
A new ATPG method for efficient capture power reduction during scan testing

Xiaoqing Wen;S. Kajihara;K. Miyase;T. Suzuki

123
Citations
On identifying don't care inputs of test patterns for combinational circuits

Seiji Kajihara;Kohei Miyase

115
Citations
A novel scheme to reduce power supply noise for high-quality at-speed scan testing

Xiaoqing Wen;K. Miyase;S. Kajihara;T. Suzuki

98
Citations
Compact test sets for high defect coverage

S.M. Reddy;I. Pomeranz;S. Kajihara

91
Citations
Selection of potentially testable path delay faults for test generation

A. Murakami;S. Kajihara;T. Sasao;I. Pomeranz

88
Citations
Evaluation of the statistical delay quality model

Yasuo Sato;Shuji Hamada;Toshiyuki Maeda;Atsuo Takatori

83
Citations
Critical-path-aware X-filling for effective IR-drop reduction in at-speed scan testing

Xiaoqing Wen;Kohei Miyase;Tatsuya Suzuki;Seiji Kajihara

79
Citations
Random access scan: a solution to test power, test data volume and test time

Dong Hyun Baik;K.K. Saluja;S. Kajihara

76
Citations
A method for identifying robust dependent and functionally unsensitizable paths

S. Kajihara;K. Kinoshita;I. Pomeranz;S.M. Reddy

73
Citations
On the effects of test compaction on defect coverage

S.M. Reddy;I. Pomeranz;S. Kajihara

70
Citations
On selecting testable paths in scan designs

Yun Shao;S.M. Reddy;I. Pomeranz;S. Kajihara

64
Citations
A Highly-Guided X-Filling Method for Effective Low-Capture-Power Scan Test Generation

Xiaoqing Wen;Kohei Miyase;Tatsuya Suzuki;Yuta Yamato

63
Citations
On testing of interconnect open defects in combinational logic circuits with stems of large fanout

S.M. Reddy;I. Pomeranz;Huaxing Tang;S. Kajihara

60
Citations
On compacting test sets by addition and removal of test vectors

S. Kajihara;I. Pomeranz;K. Kinoshita;S.M. Reddy

60
Citations
On per-test fault diagnosis using the X-fault model

Xiaoqing Wen;Tokiharu Miyoshi;Seiji Kajihara;Laung-Terng Wang

45
Citations
An efficient method to identify untestable path delay faults

Yun Shao;S.M. Reddy;S. Kajihara;I. Pomeranz

35
Citations

Frequent Co-Authors

Xiaoqing Wen Kyushu Institute of Technology

Kewal K. Saluja University of Wisconsin–Madison

Sudhakar M. Reddy University of Iowa

Irith Pomeranz Purdue University West Lafayette

Hans-Joachim Wunderlich University of Stuttgart

Krishnendu Chakrabarty Arizona State University

Patrick Girard Montpellier Laboratory of Informatics, Robotics and Microelectronics

Satoshi Fukumoto Tohoku University

Bernd Becker University of Freiburg

Jun Qian Zhejiang University

External Links

Personal website of Seiji Kajihara

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