2000 - IEEE Fellow For contributions to the area of automatic test pattern generation and fault simulation for digital circuits.
Wu-Tung Cheng spends much of his time researching Scan chain, Fault, Computer hardware, Electronic engineering and Embedded system. He combines subjects such as Fault coverage and Boundary scan with his study of Scan chain. The Fault study combines topics in areas such as Chain and Real-time computing.
His work deals with themes such as Reference data, Pipeline and Circuit design, which intersect with Computer hardware. His study in Electronic engineering is interdisciplinary in nature, drawing from both Design for testing, Resistor and Integrated circuit. His work is dedicated to discovering how Embedded system, Automatic test pattern generation are connected with Volume, Automatic test equipment and Computer engineering and other disciplines.
His scientific interests lie mostly in Scan chain, Fault, Electronic engineering, Algorithm and Automatic test pattern generation. The various areas that Wu-Tung Cheng examines in his Scan chain study include Chain, Computer hardware, Real-time computing, Artificial intelligence and Boundary scan. The concepts of his Computer hardware study are interwoven with issues in Test, Built-in self-test and Integrated circuit.
His Fault model study, which is part of a larger body of work in Fault, is frequently linked to Uncompressed video, bridging the gap between disciplines. His research in the fields of Logic gate overlaps with other disciplines such as Circuit extraction and Interposer. As a member of one scientific family, Wu-Tung Cheng mostly works in the field of Automatic test pattern generation, focusing on Fault coverage and, on occasion, Stuck-at fault.
Wu-Tung Cheng mostly deals with Scan chain, Algorithm, Fault, Chain and Artificial intelligence. His Scan chain study combines topics in areas such as Artificial neural network, Real-time computing and Benchmark. His Algorithm research includes elements of Volume, Memory array and Automatic test pattern generation.
He merges Fault with Pattern generation in his research. His research investigates the connection between Data mining and topics such as Integrated circuit that intersect with problems in Computer hardware. His biological study spans a wide range of topics, including Embedded system, Timing failure and Boundary scan.
Wu-Tung Cheng mainly focuses on Fault, Chip, Pattern recognition, Artificial intelligence and Scan chain. His studies deal with areas such as Computer hardware, Clock signal and Integrated circuit as well as Fault. His work carried out in the field of Chip brings together such families of science as Design for testing, Static random-access memory, Test compression, Semiconductor device fabrication and Transistor.
His Pattern recognition research includes themes of Artificial neural network, Algorithm design, Key and Domain knowledge. Wu-Tung Cheng has included themes like Probabilistic analysis of algorithms, Statistical classification, Unsupervised learning, Code coverage and Root cause analysis in his Algorithm design study. His study in Scan chain is interdisciplinary in nature, drawing from both Load modeling, Silicon debug and Resolution.
This overview was generated by a machine learning system which analysed the scientist’s body of work. If you have any feedback, you can contact us here.
Optimal core wrapper width selection and SOC test scheduling based on 3-D bin packing algorithm
Yu Huang;S.M. Reddy;Wu-Tung Cheng;P. Reuter.
international test conference (2002)
Resource allocation and test scheduling for concurrent test of core-based SOC design
Yu Huang;Wu-Tung Cheng;Chien-Chung Tsai;N. Mukherjee.
asian test symposium (2001)
Full-speed BIST controller for testing embedded synchronous memories
Wu-Tung Cheng;Christopher John Hill;Omar Kebichi.
X-filter: filtering unknowns from compacted test responses
Manish Sharma;Wu-Tung Cheng.
international test conference (2005)
Using constrained scan cells to test integrated circuits
Thomas Hans Rinderknecht;Wu-Tung Cheng.
Statistical diagnosis for intermittent scan chain hold-time fault
Yu Huang;Wu-Tung Cheng;S.M. Reddy;Cheng-Ju Hsieh.
international test conference (2003)
Testing embedded memories in an integrated circuit
Don E. Ross;Xiaogang Du;Wu-Tung Cheng;Joseph C. Rayhawk.
Compactor independent direct diagnosis
Wu-Tung Cheng;Kun-Han Tsai;Yu Huang;N. Tamarapalli.
asian test symposium (2004)
Compactor independent direct diagnosis of test hardware
Yu Huang;Wu-Tung Cheng;Janusz Rajski.
Survey of Scan Chain Diagnosis
Yu Huang;Ruifeng Guo;Wu-Tung Cheng;J.C.-M. Li.
IEEE Design & Test of Computers (2008)
Profile was last updated on December 6th, 2021.
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