World's Best Scientists 2026 revealed!

D-Index & Metrics

Computer Science

D-Index
39
Citations
5656
World Ranking
9846
National Ranking
4146

Electronics and Electrical Engineering

D-Index
39
Citations
5603
World Ranking
4744
National Ranking
1662

Research.com Recognitions

  • 2000 - IEEE Fellow For contributions to the area of automatic test pattern generation and fault simulation for digital circuits.

Overview

Wu-Tung Cheng is affiliated with Mentor Graphics in the United States and has contributed to research primarily in the fields of engineering and computer science. Their work spans key subfields including electrical and electronic engineering, hardware and architecture, and applied mathematics.

The scientist's research interests focus on topics related to VLSI and analog circuit testing, integrated circuits and semiconductor failure analysis, VLSI and FPGA design techniques, mathematics education and pedagogy, as well as electrostatic discharge in electronics.

Wu-Tung Cheng's publication record includes articles in several notable venues:

  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
  • arXiv (Cornell University)
  • IEEE Design and Test

Recent papers authored or coauthored by Wu-Tung Cheng include:

  • "Efficient Test Compression Configuration Selection," 2021, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
  • "A Theoretical Review on Solving Algebra Problems," 2024, arXiv (Cornell University)
  • "Scan Integrity Tests for EDT Compression," 2020, IEEE Design and Test

Frequent collaborators in Cheng's research are Janusz Rajski, Chong-Siao Ye, Shi-Xuan Zheng, Fong-Jyun Tsai, and Chen Wang. Janusz Rajski stands out as a notable coauthor with multiple joint publications.

Wu-Tung Cheng has been recognized with the IEEE Fellow award in 2000, specifically acknowledging contributions to automatic test pattern generation and fault simulation for digital circuits.

Best Publications

  • PROOFS: a fast, memory-efficient sequential circuit fault simulator

    T.M. Niermann;Wu-Tung Cheng;J.H. Patel

  • Gentest: an automatic test-generation system for sequential circuits

    W.-T. Cheng;T.J. Chakraborty

  • Optimal core wrapper width selection and SOC test scheduling based on 3-D bin packing algorithm

    Yu Huang;S.M. Reddy;Wu-Tung Cheng;P. Reuter

  • On-chip comparison and response collection tools and techniques

    Nilanjan Mukherjee;Janusz Rajski;Jerzy Tyszer

  • Resource allocation and test scheduling for concurrent test of core-based SOC design

    Yu Huang;Wu-Tung Cheng;Chien-Chung Tsai;N. Mukherjee

  • Full-speed BIST controller for testing embedded synchronous memories

    Wu-Tung Cheng;Christopher John Hill;Omar Kebichi

  • Differential Fault Simulation - A Fast Method Using Minimal Memory

    Wu-Tung Cheng;Meng-Lin Yu

  • Diagnosis for wiring interconnects

    W.-T. Cheng;J.L. Lewandowski;E. Wu

  • Sequential Circuit Test Generator (STG) benchmark results

    W.-T. Cheng;S. Davidson

  • Testing embedded memories in an integrated circuit

    Don E. Ross;Xiaogang Du;Wu-Tung Cheng;Joseph C. Rayhawk

  • Survey of Scan Chain Diagnosis

    Yu Huang;Ruifeng Guo;Wu-Tung Cheng;J.C.-M. Li

  • Oscillation-Based Prebond TSV Test

    Li-Ren Huang;Shi-Yu Huang;Stephen Sunter;Kun-Han Tsai

  • X-filter: filtering unknowns from compacted test responses

    Manish Sharma;Wu-Tung Cheng

  • Full-speed field-programmable memory BIST architecture

    Xiaogang Du;N. Mukherjee;Wu-Tung Cheng;S.M. Reddy

  • Small delay testing for TSVs in 3-D ICs

    Shi-Yu Huang;Yu-Hsiang Lin;Kun-Han (Hans) Tsai;Wu-Tung Cheng

  • Statistical diagnosis for intermittent scan chain hold-time fault

    Yu Huang;Wu-Tung Cheng;S.M. Reddy;Cheng-Ju Hsieh

  • Compactor independent direct diagnosis

    Wu-Tung Cheng;Kun-Han Tsai;Yu Huang;N. Tamarapalli

  • SPLIT circuit model for test generation

    Wu-Tung Cheng

  • Using constrained scan cells to test integrated circuits

    Thomas Hans Rinderknecht;Wu-Tung Cheng

  • Compression mode diagnosis enables high volume monitoring diagnosis flow

    A. Leininger;P. Muhmenthaler;Wu-Tung Cheng;N. Tamarapalli

  • Reduced-pin-count-testing architectures for applying test patterns

    Nilanjan Mukherjee;Jay Jahangiri;Ronald Press;Wu-Tung Cheng

Frequent Co-Authors

Sudhakar M. Reddy
Sudhakar M. Reddy University of Iowa
Janusz Rajski
Janusz Rajski Siemens (Germany)
Jerzy Tyszer
Jerzy Tyszer Poznań University of Technology
Janak H. Patel
Janak H. Patel University of Illinois at Urbana-Champaign
Bernd Becker
Bernd Becker University of Freiburg
Ilia Polian
Ilia Polian University of Stuttgart
Irith Pomeranz
Irith Pomeranz Purdue University West Lafayette

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