D-Index & Metrics Best Publications
Erik Jan Marinissen

Erik Jan Marinissen

D-Index & Metrics D-index (Discipline H-index) only includes papers and citation values for an examined discipline in contrast to General H-index which accounts for publications across all disciplines.

Discipline name D-index D-index (Discipline H-index) only includes papers and citation values for an examined discipline in contrast to General H-index which accounts for publications across all disciplines. Citations Publications World Ranking National Ranking
Electronics and Electrical Engineering D-index 44 Citations 9,200 179 World Ranking 2227 National Ranking 47

Research.com Recognitions

Awards & Achievements

2011 - IEEE Fellow For contributions to modular testing of core-based system chips

Overview

What is he best known for?

The fields of study he is best known for:

  • Electrical engineering
  • Operating system
  • Integrated circuit

His primary scientific interests are in Embedded system, Design for testing, Integrated circuit design, Scalability and System testing. Erik Jan Marinissen integrates several fields in his works, including Embedded system and Reuse. His biological study spans a wide range of topics, including Automatic test equipment, Wafer-level packaging, Advanced manufacturing and Modular design.

His Integrated circuit design research also works with subjects such as

  • System on a chip which is related to area like Algorithm design, Benchmark, Computer architecture and Application-specific integrated circuit,
  • Integer programming, which have a strong connection to Test data. The various areas that he examines in his Scalability study include Heuristic and Interoperability. His work deals with themes such as Shell, Coprocessor, Terminal and Built-in self-test, which intersect with System testing.

His most cited work include:

  • Testing embedded-core based system chips (433 citations)
  • Test wrapper and test access mechanism co-optimization for system-on-chip (394 citations)
  • A structured and scalable mechanism for test access to embedded reusable cores (316 citations)

What are the main themes of his work throughout his whole career to date?

His scientific interests lie mostly in Embedded system, Design for testing, Electronic engineering, System on a chip and Automatic test pattern generation. His work focuses on many connections between Embedded system and other disciplines, such as System testing, that overlap with his field of interest in Application-specific integrated circuit. His study in Design for testing is interdisciplinary in nature, drawing from both Die, Scalability and Built-in self-test.

His studies deal with areas such as Resistor, Wafer, Stack and Integrated circuit as well as Electronic engineering. His System on a chip study deals with Parallel computing intersecting with Integer programming. His work in Automatic test pattern generation addresses issues such as Fault coverage, which are connected to fields such as Electronic circuit.

He most often published in these fields:

  • Embedded system (34.08%)
  • Design for testing (17.04%)
  • Electronic engineering (16.59%)

What were the highlights of his more recent work (between 2015-2021)?

  • Computer hardware (7.62%)
  • Electronic engineering (16.59%)
  • Magnetoresistive random-access memory (3.59%)

In recent papers he was focusing on the following fields of study:

His main research concerns Computer hardware, Electronic engineering, Magnetoresistive random-access memory, Integrated circuit and Resistor. His Computer hardware study combines topics from a wide range of disciplines, such as Product design, Modular design, Printed circuit board and Boundary scan. Erik Jan Marinissen interconnects Wafer, Software and Silicon photonics in the investigation of issues within Electronic engineering.

His Integrated circuit study combines topics in areas such as Telecommunications and Stack. His Parallel port research incorporates elements of Embedded system, Specification language and Serial port. Erik Jan Marinissen performs integrative study on Embedded system and Economic viability in his works.

Between 2015 and 2021, his most popular works were:

  • Electrical Modeling of STT-MRAM Defects (21 citations)
  • IoT: Source of test challenges (15 citations)
  • IEEE Std P1838: DfT standard-under-development for 2.5D-, 3D-, and 5.5D-SICs (13 citations)

In his most recent research, the most cited papers focused on:

  • Operating system
  • Electrical engineering
  • Integrated circuit

Erik Jan Marinissen mainly investigates Resistor, Electronic engineering, Fault modeling, Magnetoresistive random-access memory and Wafer. The study incorporates disciplines such as Fault, Visualization, Instrumentation and State in addition to Resistor. The various areas that Erik Jan Marinissen examines in his Fault study include Magnetic ram, Emphasis, Resistive touchscreen, Memory cell and Interconnection.

The Electronic engineering study combines topics in areas such as Dram, Responsivity, Silicon photonics, Software and Insertion loss. His studies deal with areas such as Reliability engineering, Random access memory, Torque and Leakage as well as Fault modeling. His Wafer research includes elements of Waveguide, Electronic circuit, Photonics and Photodetector.

This overview was generated by a machine learning system which analysed the scientist’s body of work. If you have any feedback, you can contact us here.

Best Publications

Testing embedded-core-based system chips

Y. Zorian;E.J. Marinissen;S. Dey.
IEEE Computer (1999)

1634 Citations

Test wrapper and test access mechanism co-optimization for system-on-chip

V. Iyengar;K. Chakrabarty;E.J. Marinissen.
international test conference (2001)

619 Citations

A structured and scalable mechanism for test access to embedded reusable cores

E.J. Marinissen;R. Arendsen;G. Bos;H. Dingemanse.
international test conference (1998)

453 Citations

A set of benchmarks for modular testing of SOCs

E.J. Marinissen;V. Iyengar;K. Chakrabarty.
international test conference (2002)

398 Citations

Testing 3D chips containing through-silicon vias

Erik Jan Marinissen;Yervant Zorian.
international test conference (2009)

394 Citations

Wrapper design for embedded core test

E.J. Marinissen;S.K. Goel;M. Lousberg.
international test conference (2000)

336 Citations

Scan chain design for test time reduction in core-based ICs

J. Aerts;E.J. Marinissen.
international test conference (1998)

263 Citations

Effective and efficient test architecture design for SOCs

S.K. Goel;E.J. Marinissen.
international test conference (2002)

236 Citations

On using rectangle packing for SOC wrapper/TAM co-optimization

V. Iyengar;K. Chakrabarty;E.J. Marinissen.
vlsi test symposium (2002)

229 Citations

Towards a standard for embedded core test: an example

E.J. Marinissen;Y. Zorian;R. Kapur;T. Taylor.
international test conference (1999)

223 Citations

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