2011 - IEEE Fellow For contributions to modular testing of core-based system chips
His primary scientific interests are in Embedded system, Design for testing, Integrated circuit design, Scalability and System testing. Erik Jan Marinissen integrates several fields in his works, including Embedded system and Reuse. His biological study spans a wide range of topics, including Automatic test equipment, Wafer-level packaging, Advanced manufacturing and Modular design.
His Integrated circuit design research also works with subjects such as
His scientific interests lie mostly in Embedded system, Design for testing, Electronic engineering, System on a chip and Automatic test pattern generation. His work focuses on many connections between Embedded system and other disciplines, such as System testing, that overlap with his field of interest in Application-specific integrated circuit. His study in Design for testing is interdisciplinary in nature, drawing from both Die, Scalability and Built-in self-test.
His studies deal with areas such as Resistor, Wafer, Stack and Integrated circuit as well as Electronic engineering. His System on a chip study deals with Parallel computing intersecting with Integer programming. His work in Automatic test pattern generation addresses issues such as Fault coverage, which are connected to fields such as Electronic circuit.
His main research concerns Computer hardware, Electronic engineering, Magnetoresistive random-access memory, Integrated circuit and Resistor. His Computer hardware study combines topics from a wide range of disciplines, such as Product design, Modular design, Printed circuit board and Boundary scan. Erik Jan Marinissen interconnects Wafer, Software and Silicon photonics in the investigation of issues within Electronic engineering.
His Integrated circuit study combines topics in areas such as Telecommunications and Stack. His Parallel port research incorporates elements of Embedded system, Specification language and Serial port. Erik Jan Marinissen performs integrative study on Embedded system and Economic viability in his works.
Erik Jan Marinissen mainly investigates Resistor, Electronic engineering, Fault modeling, Magnetoresistive random-access memory and Wafer. The study incorporates disciplines such as Fault, Visualization, Instrumentation and State in addition to Resistor. The various areas that Erik Jan Marinissen examines in his Fault study include Magnetic ram, Emphasis, Resistive touchscreen, Memory cell and Interconnection.
The Electronic engineering study combines topics in areas such as Dram, Responsivity, Silicon photonics, Software and Insertion loss. His studies deal with areas such as Reliability engineering, Random access memory, Torque and Leakage as well as Fault modeling. His Wafer research includes elements of Waveguide, Electronic circuit, Photonics and Photodetector.
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Testing embedded-core-based system chips
Y. Zorian;E.J. Marinissen;S. Dey.
IEEE Computer (1999)
A structured and scalable mechanism for test access to embedded reusable cores
E.J. Marinissen;R. Arendsen;G. Bos;H. Dingemanse.
international test conference (1998)
Test wrapper and test access mechanism co-optimization for system-on-chip
V. Iyengar;K. Chakrabarty;E.J. Marinissen.
international test conference (2001)
Testing 3D chips containing through-silicon vias
Erik Jan Marinissen;Yervant Zorian.
international test conference (2009)
A set of benchmarks for modular testing of SOCs
E.J. Marinissen;V. Iyengar;K. Chakrabarty.
international test conference (2002)
Wrapper design for embedded core test
E.J. Marinissen;S.K. Goel;M. Lousberg.
international test conference (2000)
Scan chain design for test time reduction in core-based ICs
J. Aerts;E.J. Marinissen.
international test conference (1998)
Effective and efficient test architecture design for SOCs
S.K. Goel;E.J. Marinissen.
international test conference (2002)
Towards a standard for embedded core test: an example
E.J. Marinissen;Y. Zorian;R. Kapur;T. Taylor.
international test conference (1999)
On using rectangle packing for SOC wrapper/TAM co-optimization
V. Iyengar;K. Chakrabarty;E.J. Marinissen.
vlsi test symposium (2002)
Duke University
Delft University of Technology
Interuniversity Microelectronics Centre
Eindhoven University of Technology
National Tsing Hua University
North Carolina State University
KU Leuven
University of California, San Diego
University of Michigan–Ann Arbor
Arm Ltd.
Profile was last updated on December 6th, 2021.
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