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Erik Jan Marinissen

Erik Jan Marinissen

D-Index & Metrics

Electronics and Electrical Engineering

D-Index
49
Citations
10124
World Ranking
2926
National Ranking
63

Research.com Recognitions

  • 2011 - IEEE Fellow For contributions to modular testing of core-based system chips

Overview

Erik Jan Marinissen is affiliated with Imec in Belgium, focusing on research in engineering and computer science, with an emphasis on electrical and electronic engineering and hardware architecture. Their work spans topics including VLSI and analog circuit testing, integrated circuits and semiconductor failure analysis, 3D IC and TSV technologies, as well as magnetic properties of thin films and semiconductor materials and devices.

Their recent publications highlight a focus on advanced semiconductor device testing, modeling, and design. Notable papers include:

  • "Survey on STT-MRAM Testing: Failure Mechanisms, Fault Models, and Tests" (2020, arXiv (Cornell University))
  • "A Bypassable Scan Flip-Flop for Low Power Testing With Data Retention Capability" (2021, IEEE Transactions on Circuits & Systems II Express Briefs)
  • "MFA-MTJ Model: Magnetic-Field-Aware Compact Model of pMTJ for Robust STT-MRAM Design" (2022, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems)
  • "IEEE Standard 1838 Is on the Move" (2021, Computer)
  • "Characterization, Modeling, and Test of Intermediate State Defects in STT-MRAMs" (2021, IEEE Transactions on Computers)

Frequent publication venues for Marinissen include:

  • IEEE Design and Test
  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
  • IEEE Transactions on Circuits & Systems II Express Briefs
  • IEEE Transactions on Computers
  • Computer

Collaborations form an integral part of Marinissen's work. Frequent co-authors include Lizhou Wu, Siddharth Rao, Mottaqiallah Taouil, Said Hamdioui, and Francesco Lorenzelli.

Marinissen's research contributions have been recognized by the IEEE, where they were named an IEEE Fellow in 2011 for contributions to modular testing of core-based system chips.

Best Publications

  • Testing embedded-core-based system chips

    Y. Zorian;E.J. Marinissen;S. Dey

  • Test wrapper and test access mechanism co-optimization for system-on-chip

    V. Iyengar;K. Chakrabarty;E.J. Marinissen

  • A structured and scalable mechanism for test access to embedded reusable cores

    E.J. Marinissen;R. Arendsen;G. Bos;H. Dingemanse

  • A set of benchmarks for modular testing of SOCs

    E.J. Marinissen;V. Iyengar;K. Chakrabarty

  • Testing 3D chips containing through-silicon vias

    Erik Jan Marinissen;Yervant Zorian

  • Wrapper design for embedded core test

    E.J. Marinissen;S.K. Goel;M. Lousberg

  • Scan chain design for test time reduction in core-based ICs

    J. Aerts;E.J. Marinissen

  • Effective and efficient test architecture design for SOCs

    S.K. Goel;E.J. Marinissen

  • On using rectangle packing for SOC wrapper/TAM co-optimization

    V. Iyengar;K. Chakrabarty;E.J. Marinissen

  • Towards a standard for embedded core test: an example

    E.J. Marinissen;Y. Zorian;R. Kapur;T. Taylor

  • A structured and scalable test access architecture for TSV-based 3D stacked ICs

    Erik Jan Marinissen;Jouke Verbree;Mario Konijnenburg

  • On IEEE P1500's Standard for Embedded Core Test

    Erik Jan Marinissen;Rohit Kapur;Maurice Lousberg;Teresa McLaurin

  • Test access mechanism optimization, test scheduling, and tester data volume reduction for system-on-chip

    Vikram lyengar;Krishnendu Chakrabarty;E.J. Marinissen

  • SOC test architecture design for efficient utilization of test bandwidth

    Sandeep Kumar Goel;Erik Jan Marinissen

  • The Role of Test Protocols in Automated Test Generation for Embedded-Core-Based System ICs

    Erik Jan Marinissen

  • Challenges in Embedded Memory Design and Test

    Erik Jan Marinissen;Betty Prince;Doris Keitel-Schulz;Yervant Zorian

  • Application of deterministic logic BIST on industrial circuits

    G. Kiefer;H. Vranken;E.J. Marinissen;H.-J. Wunderlich

  • Impact of 3D design choices on manufacturing cost

    Dimitrios Velenis;Michele Stucchi;Erik Jan Marinissen;Bart Swinnen

  • Efficient Wrapper/TAM Co-Optimization for Large SOCs

    V. Iyengar;K. Chakrabarty;E.J. Marinissen

  • Challenges and emerging solutions in testing TSV-based 2 1 over 2D- and 3D-stacked ICs

    Erik Jan Marinissen

Frequent Co-Authors

Krishnendu Chakrabarty
Krishnendu Chakrabarty Arizona State University
Kees Goossens
Kees Goossens Eindhoven University of Technology
Cheng-Wen Wu
Cheng-Wen Wu National Tsing Hua University
Nicola Nicolici
Nicola Nicolici McMaster University
Paul D. Franzon
Paul D. Franzon North Carolina State University
Sujit Dey
Sujit Dey University of California, San Diego

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