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Computer Science

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57
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Electronics and Electrical Engineering

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57
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2001
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Research.com Recognitions

  • 2006 - IEEE Fellow For contributions to physical design automation of very large scale integrated (VLSI) circuits.

Overview

Charles J. Alpert is affiliated with Cadence Design Systems in the United States. Their professional focus lies within the domain of physical design automation for very large scale integrated (VLSI) circuits.

In 2006, Charles J. Alpert was recognized as an IEEE Fellow for contributions to this area of research, specifically for advancements related to physical design automation of VLSI circuits.

There are no recent papers, coauthors, or frequent publication venues listed for this scientist. Additionally, no book publications, specific fields or subfields of study, or detailed main research topics are available in the source data.

Best Publications

  • Recent directions in netlist partitioning: a survey

    Charles J. Alpert;Andrew B. Kahng

  • Multilevel circuit partitioning

    C.J. Alpert;Jen-Hsin Huang;A.B. Kahng

  • Buffer insertion for noise and delay optimization

    C.J. Alpert;A. Devgan;S.T. Quay

  • The ISPD98 circuit benchmark suite

    Charles J. Alpert

  • A clock distribution network for microprocessors

    P.J. Restle;T.G. McNamara;D.A. Webber;P.J. Camporese

  • Handbook of Algorithms for Physical Design Automation

    Charles J. Alpert;Dinesh P. Mehta;Sachin S. Sapatnekar

  • A practical methodology for early buffer and wire resource allocation

    C.J. Alpert;Jiang Hu;S.S. Sapatnekar;P.G. Villarrubia

  • Wire segmenting for improved buffer insertion

    Charles Alpert;Anirudh Devgan

  • Spectral Partitioning: The More Eigenvectors, The Better

    Charles J. Alpert;So-Zen Yao

  • Spectral partitioning with multiple eigenvectors

    Charles J. Alpert;Andrew B. Kahng;So-Zen Yao

  • The ISPD2005 placement contest and benchmark suite

    Gi-Joon Nam;Charles J. Alpert;Paul Villarrubia;Bruce Winter

  • RC delay metrics for performance optimization

    C.J. Alpert;A. Devgan;C.V. Kashyap

  • Buffer insertion with accurate gate and interconnect delay computation

    Charles J. Alpert;Anirudh Devgan;Stephen T. Quay

  • Porosity-aware buffered Steiner tree construction

    C.J. Alpert;G. Gandham;M. Hrkic;Jiang Hu

  • Prim-Dijkstra tradeoffs for improved performance-driven routing tree design

    C.J. Alpert;T.C. Hu;J.H. Huang;A.B. Kahng

  • The ISPD-2011 routability-driven placement contest and benchmark suite

    Natarajan Viswanathan;Charles J. Alpert;Cliff Sze;Zhuo Li

  • The DAC 2012 routability-driven placement contest and benchmark suite

    Natarajan Viswanathan;Charles Alpert;Cliff Sze;Zhuo Li

  • Fast Algorithms for Slew-Constrained Minimum Cost Buffering

    Shiyan Hu;C.J. Alpert;Jiang Hu;S.K. Karandikar

  • A delay metric for RC circuits based on the Weibull distribution

    F. Liu;C. Kashyap;C.J. Alpert

  • A semi-persistent clustering technique for VLSI circuit placement

    Charles Alpert;Andrew Kahng;Gi-Joon Nam;Sherief Reda

  • A clock distribution network for microprocessors

    P.J. Restle;T.G. McNamara;D.A. Webber;P.J. Camporese

Frequent Co-Authors

Andrew B. Kahng
Andrew B. Kahng University of California, San Diego
Jiang Hu
Jiang Hu Texas A&M University
Anirudh Devgan
Anirudh Devgan Cadence Design Systems
Sachin S. Sapatnekar
Sachin S. Sapatnekar University of Minnesota
David Z. Pan
David Z. Pan The University of Texas at Austin
Igor L. Markov
Igor L. Markov Synopsys (United States)
Bei Yu
Bei Yu Chinese University of Hong Kong
Chris Chu
Chris Chu Iowa State University
Phillip J. Restle
Phillip J. Restle IBM (United States)
Tony F. Chan
Tony F. Chan University of California, Los Angeles

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