The scientist’s investigation covers issues in Electronic engineering, Electrical engineering, Microprocessor, Transistor and Chip. His work on Very-large-scale integration as part of general Electronic engineering study is frequently linked to Skew, therefore connecting diverse disciplines of science. The Electrical engineering study which covers Optoelectronics that intersects with Channel length modulation.
His Microprocessor study combines topics in areas such as CPU multiplier, Physical design and Clock gating. The study incorporates disciplines such as Phase-locked loop, IBM and Noise in addition to Chip. His work carried out in the field of Clock network brings together such families of science as Clock domain crossing, Topology and Digital clock manager.
Phillip J. Restle spends much of his time researching Electronic engineering, Electrical engineering, Clock skew, Microprocessor and Clock domain crossing. His Electronic engineering research includes elements of Electronic circuit, Chip, Digital clock manager, Interconnection and Inductance. His work in Electrical engineering tackles topics such as Optoelectronics which are related to areas like Transconductance, Field-effect transistor and Substrate.
His Clock skew research includes themes of Grid, Synchronous circuit and Topology. His research investigates the link between Microprocessor and topics such as Integrated circuit design that cross with problems in Very-large-scale integration. He interconnects CPU multiplier and System on a chip in the investigation of issues within Clock gating.
His main research concerns Electronic engineering, Clock skew, Electrical engineering, Clock signal and Clock gating. His Electronic engineering research incorporates themes from Electronic circuit, Microprocessor, Inductor, Chip and POWER8. The concepts of his Clock skew study are interwoven with issues in Synchronous circuit and Clock domain crossing.
His research investigates the connection between Clock domain crossing and topics such as Digital clock manager that intersect with problems in Timing failure. His Voltage and Noise study in the realm of Electrical engineering connects with subjects such as Design tool and Sink. His work in Clock gating covers topics such as CPU multiplier which are related to areas like Integrated circuit.
His scientific interests lie mostly in Electronic engineering, Clock domain crossing, Clock skew, Synchronous circuit and Clock signal. Logic gate is the focus of his Electronic engineering research. His work investigates the relationship between Clock domain crossing and topics such as Digital clock manager that intersect with problems in Clock synchronization, Asynchronous circuit and Self-clocking signal.
Phillip J. Restle usually deals with Clock signal and limits it to topics linked to Inductor and Capacitor. His studies deal with areas such as Electronic circuit and Integrated circuit as well as CPU multiplier. His studies in eDRAM integrate themes in fields like Microprocessor and Computer hardware.
This overview was generated by a machine learning system which analysed the scientist’s body of work. If you have any feedback, you can contact us here.
When are transmission-line effects important for on-chip interconnections?
A. Deutsch;G.V. Kopcsay;P.J. Restle;H.H. Smith.
IEEE Transactions on Microwave Theory and Techniques (1997)
A clock distribution network for microprocessors
P.J. Restle;T.G. McNamara;D.A. Webber;P.J. Camporese.
IEEE Journal of Solid-state Circuits (2001)
SiGe-channel heterojunction p-MOSFET's
S. Verdonckt-Vandebroek;E.F. Crabbe;B.S. Meyerson;D.L. Harame.
IEEE Transactions on Electron Devices (1994)
A new 'shift and ratio' method for MOSFET channel-length extraction
Y. Taur;D.S. Zicherman;D.R. Lombardi;P.J. Restle.
IEEE Electron Device Letters (1992)
The circuit and physical design of the POWER4 microprocessor
J. D. Warnock;J. M. Keaty;J. Petrovick;J. G. Clabes.
Ibm Journal of Research and Development (2002)
Design and implementation of the POWER5/spl trade/ microprocessor
J. Clabes;J. Friedrich;M. Sweet;J. DiLullo.
international solid-state circuits conference (2004)
Design and implementation of the POWER5 microprocessor
Joachim Clabes;Joshua Friedrich;Mark Sweet;Jack DiLullo.
design automation conference (2004)
Physical design of a fourth-generation POWER GHz microprocessor
C.J. Anderson;J. Petrovick;J.M. Keaty;J. Warnock.
Designing the best clock distribution network
P.J. Restle;A. Deutsch.
symposium on vlsi circuits (1998)
X-Y grid tree clock distribution network with tunable tree and grid networks
Peter J. Camporese;Alina Deutsch;Timothy Gerard McNamara;Phillip John Restle.
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