World's Best Scientists 2026 revealed!
Alper Buyuktosunoglu

Alper Buyuktosunoglu

D-Index & Metrics

Computer Science

D-Index
38
Citations
7622
World Ranking
10097
National Ranking
4259

Electronics and Electrical Engineering

D-Index
35
Citations
7374
World Ranking
5461
National Ranking
1872

Overview

Alper Buyuktosunoglu is affiliated with IBM in the United States and conducts research primarily in computer science and engineering. Their work encompasses areas such as hardware and architecture, electrical and electronic engineering, computer networks and communications, artificial intelligence, and computer vision and pattern recognition.

The scientist has contributed extensively to topics including parallel computing and optimization techniques, low-power high-performance VLSI design, interconnection networks and systems, advanced data storage technologies, real-time systems scheduling, semiconductor materials and devices, and security and verification in computing.

Recent papers authored by or associated with Alper Buyuktosunoglu include:

  • Investigating the Effects of Task Scheduling on Thermal Behavior (2024), SSRN Electronic Journal
  • HeapCheck: Low-cost Hardware Support for Memory Safety (2022), ACM Transactions on Architecture and Code Optimization
  • IBM Telum: a 16-Core 5+ GHz DCM (2022), 2022 IEEE International Solid-State Circuits Conference (ISSCC)
  • Proactive power management in IBM z15 (2020), IBM Journal of Research and Development
  • Heterogeneity-Aware Scheduling on SoCs for Autonomous Vehicles (2021), IEEE Computer Architecture Letters

Frequent co-authors collaborating with Buyuktosunoglu include:

  • Pradip Bose
  • Subhankar Pal
  • John-David Wellman
  • Ramon Bertran
  • Aporva Amarnath

Common venues for publication show a focus on reputable journals and conferences in the field:

  • arXiv (Cornell University)
  • IEEE Computer Architecture Letters
  • ACM Transactions on Architecture and Code Optimization
  • IEEE Journal of Solid-State Circuits
  • SSRN Electronic Journal

The publication record highlights a consistent interest in advanced architectural designs, optimization of computing processes, and hardware efficiency improvements. The mix of journals and conference papers indicates engagement with both industry-oriented and academic research communities.

Best Publications

  • An Analysis of Efficient Multi-Core Global Power Management Policies: Maximizing Performance for a Given Power Budget

    C. Isci;A. Buyuktosunoglu;C.-Y. Chen;P. Bose

  • Power-aware microarchitecture: design and modeling challenges for next-generation microprocessors

    D.M. Brooks;P. Bose;S.E. Schuster;H. Jacobson

  • Microarchitectural techniques for power gating of execution units

    Zhigang Hu;Alper Buyuktosunoglu;Viji Srinivasan;Victor Zyuban

  • Memory hierarchy reconfiguration for energy and performance in general-purpose processor architectures

    Rajeev Balasubramonian;David Albonesi;Alper Buyuktosunoglu;Sandhya Dwarkadas

  • NDC: Analyzing the impact of 3D-stacked memory+logic devices on MapReduce workloads

    Seth H. Pugsley;Jeffrey Jestes;Huihui Zhang;Rajeev Balasubramonian

  • An adaptive issue queue for reduced power at high performance

    Alper Buyuktosunoglu;Stanley Schuster;David Brooks;Pradip Bose

  • Dynamically tuning processor resources with adaptive processing

    D.H. Albonesi;R. Balasubramonian;S.G. Dropsbo;S. Dwarkadas

  • Integrating adaptive on-chip storage structures for reduced dynamic power

    S. Dropsho;A. Buyuktosunoglu;R. Balasubramonian;D.H. Albonesi

  • Introducing the Adaptive Energy Management Features of the Power7 Chip

    M Floyd;M Allen-Ware;K Rajamani;B Brock

  • Dynamic power gating with quality guarantees

    Anita Lungu;Pradip Bose;Alper Buyuktosunoglu;Daniel J. Sorin

  • A circuit level implementation of an adaptive issue queue for power-aware microprocessors

    Alper Buyuktosunoglu;David Albonesi;Stanley Schuster;David Brooks

  • Long-term workload phases: duration predictions and applications to DVFS

    C. Isci;A. Buyuktosunoglu;M. Martonosi

  • Energy efficient co-adaptive instruction fetch and issue

    Alper Buyuktosunoglu;Tejas Karkhanis;David H. Albonesi;Pradip Bose

  • Systems and methods for thread assignment and core turn-off for integrated circuit energy efficiency and high-performance

    Pradip Bose;Alper Buyuktosunoglu;Eren Kursun

  • A case for guarded power gating for multi-core processors

    Niti Madan;Alper Buyuktosunoglu;Pradip Bose;Murali Annavaram

  • Voltage Noise in Multi-Core Processors: Empirical Characterization and Optimization Opportunities

    Ramon Bertran;Alper Buyuktosunoglu;Pradip Bose;Timothy J. Slegel

  • Safe limits on voltage reduction efficiency in GPUs: a direct measurement approach

    Jingwen Leng;Alper Buyuktosunoglu;Ramon Bertran;Pradip Bose

  • Method and system for controlling power in a chip through a power-performance monitor and control unit

    Pradip Bose;Alper Buyuktosunoglu;Chen-Yong Cher;Prabhakar N. Kudva

  • Crank it up or dial it down: coordinated multiprocessor frequency and folding control

    Augusto Vega;Alper Buyuktosunoglu;Heather Hanson;Pradip Bose

  • Comparing Implementations of Near-Data Computing with In-Memory MapReduce Workloads

    Seth H. Pugsley;Jeffrey Jestes;Rajeev Balasubramonian;Vijayalakshmi Srinivasan

Frequent Co-Authors

Pradip Bose
Pradip Bose IBM (United States)
David H. Albonesi
David H. Albonesi Cornell University
Vijayalakshmi Srinivasan
Vijayalakshmi Srinivasan IBM (United States)
David Brooks
David Brooks Harvard University
Francisco J. Cazorla
Francisco J. Cazorla Barcelona Supercomputing Center
Phillip J. Restle
Phillip J. Restle IBM (United States)
Rajeev Balasubramonian
Rajeev Balasubramonian University of Utah
Mateo Valero
Mateo Valero Barcelona Supercomputing Center
Sandhya Dwarkadas
Sandhya Dwarkadas University of Rochester
Kevin Skadron
Kevin Skadron University of Virginia

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