2022 - Research.com Computer Science in Spain Leader Award
2012 - ACM Distinguished Service Award For extraordinary leadership of initiatives in high-performance computing research and education, including the HiPEAC European Network of Excellence and the Barcelona Supercomputing Center.
2009 - Member of Academia Europaea
2007 - ACM - IEEE CS Eckert-Mauchly Award For extraordinary leadership in building a world class computer architecture research center, for seminal contributions in the areas of vector computing and multithreading, and for pioneering basic new approaches to instruction-level parallelism.
2002 - ACM Fellow For contributions to the design of vector, superscalar, and VLIW architectures, and technical leadership.
2001 - IEEE Fellow For contributions to the design of vector architectures and superscalar processors.
Mateo Valero mostly deals with Parallel computing, Operating system, Instruction set, Embedded system and Multithreading. His Parallel computing study focuses on Cache in particular. His study in Operating system is interdisciplinary in nature, drawing from both Transactional memory, Commit and Transaction processing.
His Instruction set study combines topics from a wide range of disciplines, such as Scheme and Implementation. In his study, Flexibility, Sensitivity, CPU power dissipation and Frequency scaling is strongly linked to Supercomputer, which falls under the umbrella field of Embedded system. His Processor register study incorporates themes from Register file and Instruction register.
His main research concerns Parallel computing, Embedded system, Distributed computing, Operating system and Scheduling. His Parallel computing study integrates concerns from other disciplines, such as Scalability and Thread. His research in the fields of Multithreading overlaps with other disciplines such as Fetch.
His research integrates issues of Supercomputer, Computer network and Programming paradigm in his study of Distributed computing. His biological study spans a wide range of topics, including Transactional memory, Database transaction and Register file. His research in Instruction set intersects with topics in Software and Processor register.
Mateo Valero spends much of his time researching Parallel computing, Distributed computing, Embedded system, Scheduling and Runtime system. His work deals with themes such as Scalability, Thread and Programming paradigm, which intersect with Parallel computing. The various areas that Mateo Valero examines in his Distributed computing study include Supercomputer, Adaptive routing and Node, Computer network, Interconnection.
His work carried out in the field of Embedded system brings together such families of science as Dram, Interleaved memory and Memory controller. His research investigates the connection between Scheduling and topics such as Multi-core processor that intersect with issues in Energy accounting. His Runtime system research also works with subjects such as
His primary scientific interests are in Parallel computing, Distributed computing, Runtime system, Supercomputer and Scalability. His Parallel computing research is multidisciplinary, relying on both Scheduling and Thread. His Distributed computing research includes themes of System software, Network topology, Computer network, Interconnection and Programming paradigm.
His Runtime system research integrates issues from Computer architecture, Source code, Exploit, Multi-core processor and Data structure. His studies in Supercomputer integrate themes in fields like Domain, Xeon Phi, Leverage, Parallel processing and Flexibility. The concepts of his Scalability study are interwoven with issues in Software and Software deployment.
This overview was generated by a machine learning system which analysed the scientist’s body of work. If you have any feedback, you can contact us here.
The International Exascale Software Project roadmap
Jack Dongarra;Pete Beckman;Terry Moore;Patrick Aerts.
ieee international conference on high performance computing data and analytics (2011)
Multiple-banked register file architectures
José-Lorenzo Cruz;Antonio González;Mateo Valero;Nigel P. Topham.
international symposium on computer architecture (2000)
A data cache with multiple caching strategies tuned to different types of locality
Antonio González;Carlos Aliagas;Mateo Valero.
international conference on supercomputing (1995)
Hardware support for WCET analysis of hard real-time multicore systems
Marco Paolieri;Eduardo Quiñones;Francisco J. Cazorla;Guillem Bernat.
international symposium on computer architecture (2009)
Parallel Computer Architecture
Silvia M. Müller;Per Stenström;Mateo Valero;Stamatis Vassiliadis.
european conference on parallel processing (2000)
Performance, power efficiency and scalability of asymmetric cluster chip multiprocessors
T.Y. Morad;U.C. Weiser;A. Kolodnyt;M. Valero.
IEEE Computer Architecture Letters (2006)
Dynamically Controlled Resource Allocation in SMT Processors
Francisco J. Cazorla;Alex Ramirez;Mateo Valero;Enrique Fernandez.
international symposium on microarchitecture (2004)
Enabling preemptive multiprogramming on GPUs
Ivan Tanasic;Isaac Gelado;Javier Cabezas;Alex Ramirez.
international symposium on computer architecture (2014)
Supercomputing with commodity CPUs: are mobile SoCs ready for HPC?
Nikola Rajovic;Paul M. Carpenter;Isaac Gelado;Nikola Puzovic.
ieee international conference on high performance computing data and analytics (2013)
Fuzzy memoization for floating-point multimedia applications
C. Alvarez;J. Corbal;M. Valero.
IEEE Transactions on Computers (2005)
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