World's Best Scientists 2026 revealed!

D-Index & Metrics

Computer Science

D-Index
50
Citations
10743
World Ranking
5593
National Ranking
30

Research.com Recognitions

  • 2010 - Member of Academia Europaea
  • 2008 - ACM Fellow For contributions to the design of high-performance memory systems.
  • 2007 - IEEE Fellow For contributions to design of high-performance memory systems

Overview

Per Stenström is affiliated with Chalmers University of Technology in Sweden. Their research work primarily involves several fields within computer science and engineering, with a focus on distributed and parallel computing systems, real-time systems scheduling, and hardware-related topics.

The main fields of study associated with Stenström include:

  • Computer Science
  • Engineering

Within these broad fields, their research delves into specific subfields such as:

  • Computer Networks and Communications
  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Industrial and Manufacturing Engineering
  • Information Systems

Their research topics are detailed through areas like:

  • Distributed and Parallel Computing Systems
  • Real-Time Systems Scheduling
  • Interconnection Networks and Systems
  • Scheduling and Optimization Algorithms
  • Cloud Computing and Resource Management
  • Parallel Computing and Optimization Techniques
  • Distributed systems and fault tolerance

Stenström's recent publications further reflect these themes, including:

  • "Bounding the execution time of parallel applications on unrelated multiprocessors," 2021, Real-Time Systems
  • "Federated Scheduling of Sporadic DAGs on Unrelated Multiprocessors," 2021, ACM Transactions on Embedded Computing Systems
  • "CBP: Coordinated management of cache partitioning, bandwidth partitioning and prefetch throttling," 2021, arXiv (Cornell University)
  • "SoK: Analysis of Root Causes and Defense Strategies for Attacks on Microarchitectural Optimizations," 2022, arXiv (Cornell University)

The frequent co-authors with whom Stenström has collaborated include:

  • Petros Voudouris
  • Risat Mahmud Pathan
  • Nadja Ramhöj Holtryd
  • Madhavan Manivannan
  • Miquel Pericàs

Publication venues prominently featuring Stenström's work are:

  • arXiv (Cornell University)
  • Real-Time Systems
  • ACM Transactions on Embedded Computing Systems

Stenström has been recognized with several awards during their career, including:

  • Member of Academia Europaea (2010)
  • ACM Fellow (2008) for contributions to the design of high-performance memory systems
  • IEEE Fellow (2007) for contributions to design of high-performance memory systems

Best Publications

  • The worst-case execution-time problem—overview of methods and survey of tools

    Reinhard Wilhelm;Jakob Engblom;Andreas Ermedahl;Niklas Holsti

  • A survey of cache coherence schemes for multiprocessors

    P. Stenstrom

  • Timing anomalies in dynamically scheduled microprocessors

    T. Lundqvist;P. Stenstrom

  • Parallel Computer Architecture

    Silvia M. Müller;Per Stenström;Mateo Valero;Stamatis Vassiliadis

  • An adaptive cache coherence protocol optimized for migratory sharing

    Per Stenström;Mats Brorsson;Lars Sandberg

  • A Robust Main-Memory Compression Scheme

    Magnus Ekman;Per Stenstrom

  • Sequential hardware prefetching in shared-memory multiprocessors

    F. Dahlgren;M. Dubois;P. Stenstrom

  • Comparative performance evaluation of cache-coherent NUMA and COMA architectures

    Per Stenström;Truman Joe;Anoop Gupta

  • An Integrated Path and Timing Analysis Method based on Cycle-Level Symbolic Execution

    Thomas Lundqvist;Per Stenström

  • SimICS/sun4m: a virtual workstation

    Peter S. Magnusson;Fredrik Dahlgren;Håkan Grahn;Magnus Karlsson

  • Fixed and Adaptive Sequential Prefetching in Shared Memory Multiprocessors

    Fredrik Dahlgren;Michel Dubois;Per Stenstrom

  • An Adaptive Shared/Private NUCA Cache Partitioning Scheme for Chip Multiprocessors

    H. Dybdahl;P. Stenstrom

  • Recency-based TLB preloading

    Ashley Saulsbury;Fredrik Dahlgren;Per Stenström

  • A prefetching technique for irregular accesses to linked data structures

    M. Karlsson;F. Dahlgren;P. Stenstrom

  • The detection and elimination of useless misses in multiprocessors

    Michel Dubois;Jonas Skeppstedt;Livio Ricciulli;Krishnan Ramamurthy

  • SC2: a statistical compression cache scheme

    Angelos Arelakis;Per Stenstrom

  • The Cachemire Test Bench A Flexible And Effective Approach For Simulation Of Multiprocessors

    M. Brorsson;F. Dahlgren;H. Nilsson;P. Stenstrom

  • TLB and snoop energy-reduction using virtual caches in low-power chip-multiprocessors

    Magnus Ekman;Per Stenström;Fredrik Dahlgren

  • Integrating Path and Timing Analysis Using Instruction-Level Simulation Techniques

    Thomas Lundqvist;Per Stenström

  • Moving from petaflops to petadata

    Michael J. Flynn;Oskar Mencer;Veljko Milutinovic;Goran Rakocevic

  • Evaluation of hardware-based stride and sequential prefetching in shared-memory multiprocessors

    F. Dahlgren;P. Stenstrom

Frequent Co-Authors

Murali Annavaram
Murali Annavaram University of Southern California
Mateo Valero
Mateo Valero Barcelona Supercomputing Center
Koen De Bosschere
Koen De Bosschere Ghent University
James E. Smith
James E. Smith University of Wisconsin–Madison
David Whalley
David Whalley Florida State University
Alex Ramirez
Alex Ramirez Google (United States)
Sally A. McKee
Sally A. McKee Chalmers University of Technology
André Seznec
André Seznec French Institute for Research in Computer Science and Automation - INRIA
Stefanos Kaxiras
Stefanos Kaxiras Uppsala University
Frank Mueller
Frank Mueller North Carolina State University

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