2016 - ACM Fellow For contributions to branch prediction and cache memory design.
André Seznec focuses on Parallel computing, Branch predictor, Algorithm, Branch target predictor and Cache. André Seznec performs integrative Parallel computing and Throughput research in his work. André Seznec undertakes interdisciplinary study in the fields of Branch predictor and Alpha through his research.
André Seznec studied Branch target predictor and Pipeline that intersect with CPU cache. His studies deal with areas such as Microprocessor, Reduction, Code, Redundancy and Aliasing as well as Instructions per cycle. His research integrates issues of Assembly language, CUDA and Source code in his study of Instruction set.
André Seznec mostly deals with Parallel computing, Cache, Branch predictor, Microarchitecture and Multi-core processor. André Seznec conducts interdisciplinary study in the fields of Parallel computing and Fetch through his research. His Cache research is multidisciplinary, incorporating perspectives in Distributed computing, Loop tiling and Speedup.
His studies in Branch predictor integrate themes in fields like Branch target predictor, Statistics, Branch and Algorithm. His Microarchitecture research focuses on Instruction set and how it relates to Microprocessor. His Multi-core processor research includes themes of Amdahl's law and Workload.
Parallel computing, Microarchitecture, Multi-core processor, Cache and Out-of-order execution are his primary areas of study. His study in Parallel computing is interdisciplinary in nature, drawing from both Programming language and Thread. André Seznec interconnects Value, Operand, Computer architecture and Superscalar in the investigation of issues within Microarchitecture.
His Multi-core processor research incorporates elements of Instruction window, Distributed computing, Embedded system, Memory bandwidth and Speedup. His study on Out-of-order execution also encompasses disciplines like
The scientist’s investigation covers issues in Parallel computing, Set, Branch predictor, Smart Cache and Page cache. The concepts of his Parallel computing study are interwoven with issues in Thread and Source code. His Set study incorporates themes from Power efficient, Page and Translation lookaside buffer.
His Branch predictor research is multidisciplinary, relying on both Interpreter, Indirect branch, Computer engineering and Component. The Smart Cache study combines topics in areas such as Cache pollution, Cache-oblivious algorithm and Cache invalidation. His Page cache study combines topics from a wide range of disciplines, such as Write-once, Pipeline burst cache and Cache coloring.
This overview was generated by a machine learning system which analysed the scientist’s body of work. If you have any feedback, you can contact us here.
A case for two-way skewed-associative caches
international symposium on computer architecture (1993)
Design tradeoffs for the alpha EV8 conditional branch predictor
André Seznec;Stephen Felix;Venkata Krishnan;Yiannakis Sazeides.
international symposium on computer architecture (2002)
Trading conflict and capacity aliasing in conditional branch predictors
Pierre Michaud;André Seznec;Richard Uhlig.
international symposium on computer architecture (1997)
A case for (partially) TAgged GEometric history length branch prediction.
André Seznec;Pierre Michaud.
Journal of Instruction-level Parallelism (2006)
Decoupled sectored caches: conciliating low tag implementation cost
international symposium on computer architecture (1994)
Analysis of the O-GEometric History Length Branch Predictor
international symposium on computer architecture (2005)
Choosing representative slices of program execution for microarchitecture simulations: a preliminary application to the data stream
Thierry Lafage;André Seznec.
Workload characterization of emerging computer applications (2001)
Performance implications of single thread migration on a chip multi-core
Theofanis Constantinou;Yiannakis Sazeides;Pierre Michaud;Damien Fetis.
ACM Sigarch Computer Architecture News (2005)
Multiple-block ahead branch predictors
André Seznec;Stéphan Jourdan;Pascal Sainrat;Pierre Michaud.
architectural support for programming languages and operating systems (1996)
Improving cache behavior of dynamically allocated data structures
D. N. Truong;F. Bodin;A. Seznec.
international conference on parallel architectures and compilation techniques (1998)
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