What is he best known for?
The fields of study he is best known for:
- Operating system
- Central processing unit
- Programming language
André Seznec focuses on Parallel computing, Branch predictor, Algorithm, Branch target predictor and Cache.
André Seznec performs integrative Parallel computing and Throughput research in his work.
André Seznec undertakes interdisciplinary study in the fields of Branch predictor and Alpha through his research.
André Seznec studied Branch target predictor and Pipeline that intersect with CPU cache.
His studies deal with areas such as Microprocessor, Reduction, Code, Redundancy and Aliasing as well as Instructions per cycle.
His research integrates issues of Assembly language, CUDA and Source code in his study of Instruction set.
His most cited work include:
- A case for two-way skewed-associative caches (282 citations)
- Design tradeoffs for the alpha EV8 conditional branch predictor (147 citations)
- Trading conflict and capacity aliasing in conditional branch predictors (143 citations)
What are the main themes of his work throughout his whole career to date?
André Seznec mostly deals with Parallel computing, Cache, Branch predictor, Microarchitecture and Multi-core processor.
André Seznec conducts interdisciplinary study in the fields of Parallel computing and Fetch through his research.
His Cache research is multidisciplinary, incorporating perspectives in Distributed computing, Loop tiling and Speedup.
His studies in Branch predictor integrate themes in fields like Branch target predictor, Statistics, Branch and Algorithm.
His Microarchitecture research focuses on Instruction set and how it relates to Microprocessor.
His Multi-core processor research includes themes of Amdahl's law and Workload.
He most often published in these fields:
- Parallel computing (62.94%)
- Cache (24.48%)
- Branch predictor (17.48%)
What were the highlights of his more recent work (between 2012-2020)?
- Parallel computing (62.94%)
- Microarchitecture (12.59%)
- Multi-core processor (11.19%)
In recent papers he was focusing on the following fields of study:
Parallel computing, Microarchitecture, Multi-core processor, Cache and Out-of-order execution are his primary areas of study.
His study in Parallel computing is interdisciplinary in nature, drawing from both Programming language and Thread.
André Seznec interconnects Value, Operand, Computer architecture and Superscalar in the investigation of issues within Microarchitecture.
His Multi-core processor research incorporates elements of Instruction window, Distributed computing, Embedded system, Memory bandwidth and Speedup.
His study on Out-of-order execution also encompasses disciplines like
- Overhead which connect with Binary number and Algorithm,
- Register file which connect with Resource allocation, Processor design, Critical path method and Pipeline.
His work on Cache-oblivious algorithm and Page cache is typically connected to Context as part of general Cache algorithms study, connecting several disciplines of science.
Between 2012 and 2020, his most popular works were:
- Performance upper bound analysis and optimization of SGEMM on Fermi and Kepler GPUs (75 citations)
- Skewed Compressed Caches (48 citations)
- Prediction-based superpage-friendly TLB designs (47 citations)
In his most recent research, the most cited papers focused on:
- Operating system
- Central processing unit
- Programming language
The scientist’s investigation covers issues in Parallel computing, Set, Branch predictor, Smart Cache and Page cache.
The concepts of his Parallel computing study are interwoven with issues in Thread and Source code.
His Set study incorporates themes from Power efficient, Page and Translation lookaside buffer.
His Branch predictor research is multidisciplinary, relying on both Interpreter, Indirect branch, Computer engineering and Component.
The Smart Cache study combines topics in areas such as Cache pollution, Cache-oblivious algorithm and Cache invalidation.
His Page cache study combines topics from a wide range of disciplines, such as Write-once, Pipeline burst cache and Cache coloring.
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