2017 - ACM Fellow For contributions to die-stacking technologies in computer architecture
2014 - ACM Distinguished Member
2009 - ACM Senior Member
His primary scientific interests are in Embedded system, Parallel computing, Cache, Dram and Static random-access memory. His research in the fields of Microarchitecture and Routing overlaps with other disciplines such as Stacking. His study in Parallel computing is interdisciplinary in nature, drawing from both Computer architecture, System on a chip, Central processing unit and Translation lookaside buffer.
His study involves Pipeline burst cache and Cache algorithms, a branch of Cache. Gabriel H. Loh combines subjects such as Random access memory, Memory controller, Flat memory model, Memory management and Multi-core processor with his study of Dram. Within one scientific family, Gabriel H. Loh focuses on topics pertaining to Universal memory under Static random-access memory, and may sometimes address concerns connected to Memory rank.
His primary areas of investigation include Parallel computing, Computer hardware, Cache, Embedded system and Interleaved memory. His work in Parallel computing tackles topics such as Scalability which are related to areas like Interconnection. His work deals with themes such as Dram, Multi-core processor and Static random-access memory, which intersect with Embedded system.
His studies deal with areas such as Random access memory and CAS latency as well as Dram. His Interleaved memory study incorporates themes from Registered memory, Extended memory, Memory map and Uniform memory access. His study focuses on the intersection of Cache coloring and fields such as Page cache with connections in the field of Cache-oblivious algorithm.
His primary scientific interests are in Cache, Parallel computing, Operating system, Page table and Computer network. His research on Cache focuses in particular on CPU cache. His study ties his expertise on General-purpose computing on graphics processing units together with the subject of Parallel computing.
His Scheduling study deals with Quality of service intersecting with Embedded system. His study in the fields of Field-programmable gate array under the domain of Embedded system overlaps with other disciplines such as Design process. In his research, Dram is intimately related to Electrical engineering, which falls under the overarching field of Memory bandwidth.
Gabriel H. Loh focuses on Memory management, Parallel computing, Memory bandwidth, Interleaved memory and Page table. His Memory management study combines topics in areas such as Dram, Non-volatile memory, Multi-core processor and Virtualization. His research in Dram intersects with topics in Supercomputer, Random access memory, Shared memory, Embedded system and Computer network.
His Speedup study, which is part of a larger body of work in Parallel computing, is frequently linked to Interrupt, bridging the gap between disciplines. His research investigates the link between Interleaved memory and topics such as Distributed shared memory that cross with problems in Memory map and Computer architecture. His biological study spans a wide range of topics, including Bottleneck, Virtual address space, Scheduling and SIMD.
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3D-Stacked Memory Architectures for Multi-core Processors
Gabriel H. Loh.
international symposium on computer architecture (2008)
Die Stacking (3D) Microarchitecture
Bryan Black;Murali Annavaram;Ned Brekelbaum;John DeVale.
international symposium on microarchitecture (2006)
Design space exploration for 3D architectures
Yuan Xie;Gabriel H. Loh;Bryan Black;Kerry Bernstein.
ACM Journal on Emerging Technologies in Computing Systems (2006)
Use ECP, not ECC, for hard failures in resistive memories
Stuart Schechter;Gabriel H. Loh;Karin Strauss;Doug Burger.
international symposium on computer architecture (2010)
Processor Design in 3D Die-Stacking Technologies
Gabriel H. Loh;Yuan Xie;Bryan Black.
IEEE Micro (2007)
PIPP: promotion/insertion pseudo-partitioning of multi-core shared caches
Yuejian Xie;Gabriel H. Loh.
international symposium on computer architecture (2009)
Staged memory scheduling: achieving high performance and scalability in heterogeneous systems
Rachata Ausavarungnirun;Kevin Kai-Wei Chang;Lavanya Subramanian;Gabriel H. Loh.
international symposium on computer architecture (2012)
Efficiently enabling conventional block sizes for very large die-stacked DRAM caches
Gabriel H. Loh;Mark D. Hill.
international symposium on microarchitecture (2011)
Thermal analysis of a 3D die-stacked high-performance microprocessor
Kiran Puttaswamy;Gabriel H. Loh.
great lakes symposium on vlsi (2006)
3D-MAPS: 3D Massively parallel processor with stacked memory
Dae Hyun Kim;Krit Athikulwongse;Michael Healy;Mohammad Hossain.
international solid-state circuits conference (2012)
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