World's Best Scientists 2026 revealed!

D-Index & Metrics

Computer Science

D-Index
54
Citations
11952
World Ranking
4552
National Ranking
2131

Research.com Recognitions

  • 2017 - ACM Fellow For contributions to die-stacking technologies in computer architecture
  • 2014 - ACM Distinguished Member
  • 2009 - ACM Senior Member

Overview

Gabriel H. Loh is affiliated with Advanced Micro Devices in the United States. The research contributions span multiple areas within computer science, specifically focusing on artificial intelligence, hardware and architecture, computational theory and mathematics, and electrical and electronic engineering.

The scientist's recent publications include:

  • Accelerating Variational Quantum Algorithms Using Circuit Concurrency, 2021, published in arXiv (Cornell University)
  • Interconnect Design for Heterogeneous Integration of Chiplets in the AMD Instinct MI300X Accelerator, 2024, published in IEEE Micro

Frequent co-authors in these works include:

  • Salonik Resch
  • Anthony Gutierrez
  • Joon Suk Huh
  • Srikant Bharadwaj
  • Yasuko Eckert

Gabriel H. Loh's research fields cover several specialized areas, with the number of publications indicated as follows:

  • Artificial Intelligence (2 publications)
  • Hardware and Architecture (2 publications)
  • Computational Theory and Mathematics (1 publication)
  • Electrical and Electronic Engineering (1 publication)

The scientist's main topics of work focus on:

  • Quantum Computing Algorithms and Architecture
  • Quantum-Dot Cellular Automata
  • Quantum Information and Cryptography
  • Embedded Systems Design Techniques
  • Parallel Computing and Optimization Techniques
  • 3D IC and TSV technologies

Gabriel H. Loh's research has appeared in publication venues such as arXiv (Cornell University) and IEEE Micro.

Among professional recognitions, the scientist has received:

  • ACM Fellow in 2017 for contributions to die-stacking technologies in computer architecture
  • ACM Distinguished Member in 2014
  • ACM Senior Member in 2009

Best Publications

  • 3D-Stacked Memory Architectures for Multi-core Processors

    Gabriel H. Loh

  • Die Stacking (3D) Microarchitecture

    Bryan Black;Murali Annavaram;Ned Brekelbaum;John DeVale

  • Design space exploration for 3D architectures

    Yuan Xie;Gabriel H. Loh;Bryan Black;Kerry Bernstein

  • Use ECP, not ECC, for hard failures in resistive memories

    Stuart Schechter;Gabriel H. Loh;Karin Strauss;Doug Burger

  • Processor Design in 3D Die-Stacking Technologies

    Gabriel H. Loh;Yuan Xie;Bryan Black

  • PIPP: promotion/insertion pseudo-partitioning of multi-core shared caches

    Yuejian Xie;Gabriel H. Loh

  • Fundamental Latency Trade-off in Architecting DRAM Caches: Outperforming Impractical SRAM-Tags with a Simple and Practical Design

    Moinuddin K. Qureshi;Gabe H. Loh

  • Staged memory scheduling: achieving high performance and scalability in heterogeneous systems

    Rachata Ausavarungnirun;Kevin Kai-Wei Chang;Lavanya Subramanian;Gabriel H. Loh

  • Efficiently enabling conventional block sizes for very large die-stacked DRAM caches

    Gabriel H. Loh;Mark D. Hill

  • Heterogeneous memory architectures: A HW/SW approach for mixing die-stacked and off-package memories

    Mitesh R. Meswani;Sergey Blagodurov;David Roberts;John Slice

  • Unison Cache: A Scalable and Effective Die-Stacked DRAM Cache

    Djordje Jevdjic;Gabriel H. Loh;Cansu Kaynak;Babak Falsafi

  • 3D-MAPS: 3D Massively parallel processor with stacked memory

    Dae Hyun Kim;Krit Athikulwongse;Michael Healy;Mohammad Hossain

  • Thermal Herding: Microarchitecture Techniques for Controlling Hotspots in High-Performance 3D-Integrated Processors

    K. Puttaswamy;G.H. Loh

  • Enabling interposer-based disintegration of multi-core processors

    Ajaykumar Kannan;Natalie Enright Jerger;Gabriel H. Loh

  • Increasing TLB reach by exploiting clustering in page translations

    Binh Pham;Abhishek Bhattacharjee;Yasuko Eckert;Gabriel H. Loh

  • Zesto: A cycle-level simulator for highly detailed microarchitecture exploration

    Gabriel H. Loh;Samantika Subramaniam;Yuejian Xie

  • Managing GPU Concurrency in Heterogeneous Architectures

    Onur Kayiran;Nachiappan Chidambaram Nachiappan;Adwait Jog;Rachata Ausavarungnirun

  • Pioneering Chiplet Technology and Design for the AMD EPYC™ and Ryzen™ Processor Families : Industrial Product

    Samuel Naffziger;Noah Beck;Thomas Burd;Kevin Lepak

  • Implementing caches in a 3D technology for high performance processors

    K. Puttaswamy;G.H. Loh

  • Multiobjective Microarchitectural Floorplanning for 2-D and 3-D ICs

    M. Healy;M. Vittes;M. Ekpanyapong;C.S. Ballapuram

  • Adaptive Caches: Effective Shaping of Cache Behavior to Workloads

    Ranjith Subramanian;Yannis Smaragdakis;Gabriel H. Loh

Frequent Co-Authors

Michael J. Schulte
Michael J. Schulte Advanced Micro Devices (United States)
Yuan Xie
Yuan Xie Hong Kong University of Science and Technology
Onur Mutlu
Onur Mutlu ETH Zurich
Sung Kyu Lim
Sung Kyu Lim Georgia Institute of Technology
Natalie Enright Jerger
Natalie Enright Jerger University of Toronto
Mark D. Hill
Mark D. Hill University of Wisconsin–Madison
Hsien-Hsin S. Lee
Hsien-Hsin S. Lee Intel (United States)
Chita R. Das
Chita R. Das Pennsylvania State University
Babak Falsafi
Babak Falsafi École Polytechnique Fédérale de Lausanne
Steven K. Reinhardt
Steven K. Reinhardt Advanced Micro Devices (United States)

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