Jung Ho Ahn spends much of his time researching Computer architecture, Embedded system, Dram, Cache and Multi-core processor. The study incorporates disciplines such as Configuration management and Concurrency in addition to Computer architecture. His Embedded system study combines topics in areas such as Photonics, Thread and Multiplexing, Chip, Electrical engineering.
His Dram research includes themes of Universal memory and Memory rank. His Cache research is multidisciplinary, incorporating perspectives in Manycore processor and Random access memory. His Manycore processor study also includes
His primary areas of investigation include Parallel computing, Dram, Embedded system, Computer hardware and Cache. The concepts of his Dram study are interwoven with issues in Latency, Memory rank, Static random-access memory, Universal memory and CAS latency. His research integrates issues of Data transmission, Interleaved memory, Conventional memory, Registered memory and Efficient energy use in his study of Embedded system.
He has included themes like Computer architecture and Multi-core processor in his Cache study. Jung Ho Ahn interconnects Manycore processor and Usability in the investigation of issues within Computer architecture. His research in Multi-core processor focuses on subjects like Multiprocessing, which are connected to Design space exploration and Overhead.
Dram, Parallel computing, Embedded system, Server and Cache are his primary areas of study. His Dram research integrates issues from CAS latency, Efficient energy use and Data transmission. In his study, Dram cache, Pipeline burst cache, Computer architecture and Bandwidth is strongly linked to Static random-access memory, which falls under the umbrella field of CAS latency.
His work on Memory hierarchy as part of his general Parallel computing study is frequently connected to Multiplication and Throughput, thereby bridging the divide between different branches of science. As a part of the same scientific family, Jung Ho Ahn mostly works in the field of Embedded system, focusing on Latency and, on occasion, Random access and Response time. His study in Workload is interdisciplinary in nature, drawing from both Isolation, Multiprocessing and Multi-core processor.
His main research concerns Dram, Row, Computer hardware, Parallel computing and Normalization. His Dram study combines topics in areas such as Efficient energy use and Reliability. Jung Ho Ahn has researched Reliability in several fields, including Decoding methods, Embedded system, Access time and Resilience.
His Row research overlaps with Energy, Probabilistic logic and Cache. Many of his research projects under Parallel computing are closely connected to Smoothing with Smoothing, tying the diverse disciplines of science together. Jung Ho Ahn has included themes like Speech recognition and Convolutional neural network in his Normalization study.
This overview was generated by a machine learning system which analysed the scientist’s body of work. If you have any feedback, you can contact us here.
McPAT: an integrated power, area, and timing modeling framework for multicore and manycore architectures
Sheng Li;Jung Ho Ahn;Richard D. Strong;Jay B. Brockman.
international symposium on microarchitecture (2009)
Corona: System Implications of Emerging Nanophotonic Technology
Dana Vantrease;Robert Schreiber;Matteo Monchiero;Moray McLaren.
international symposium on computer architecture (2008)
Merrimac: Supercomputing with Streams
William J. Dally;Francois Labonte;Abhishek Das;Patrick Hanrahan.
conference on high performance computing (supercomputing) (2003)
Programmable stream processors
U.J. Kapasi;S. Rixner;W.J. Dally;B. Khailany.
IEEE Computer (2003)
A Comprehensive Memory Modeling Tool and Its Application to the Design and Analysis of Future Memory Hierarchies
Shyamkumar Thoziyoor;Jung Ho Ahn;Matteo Monchiero;Jay B. Brockman.
international symposium on computer architecture (2008)
HyperX: topology, routing, and packaging of efficient large-scale networks
Jung Ho Ahn;Nathan Binkert;Al Davis;Moray McLaren.
ieee international conference on high performance computing data and analytics (2009)
NDA: Near-DRAM acceleration architecture leveraging commodity DRAM devices and standard memory modules
Amin Farmahini-Farahani;Jung Ho Ahn;Katherine Morrow;Nam Sung Kim.
high-performance computer architecture (2015)
CACTI-P: architecture-level modeling for SRAM-based structures with advanced leakage reduction techniques
Sheng Li;Ke Chen;Jung Ho Ahn;Jay B. Brockman.
international conference on computer aided design (2011)
CACTI-3DD: architecture-level modeling for 3D die-stacked DRAM main memory
Ke Chen;Sheng Li;Naveen Muralimanohar;Jung Ho Ahn.
design, automation, and test in europe (2012)
The McPAT Framework for Multicore and Manycore Architectures: Simultaneously Modeling Power, Area, and Timing
Sheng Li;Jung Ho Ahn;Richard D. Strong;Jay B. Brockman.
ACM Transactions on Architecture and Code Optimization (2013)
If you think any of the details on this page are incorrect, let us know.
We appreciate your kind effort to assist us to improve this page, it would be helpful providing us with as much detail as possible in the text box below:
Google (United States)
Cerebras Systems
Nvidia (United Kingdom)
University of Illinois at Urbana-Champaign
University of California, Los Angeles
The University of Texas at Austin
Hewlett Packard Enterprise (United States)
Hewlett-Packard (United States)
Carnegie Mellon University
Rice University
Stanford University
University of Illinois at Urbana-Champaign
Bar-Ilan University
Heinrich Heine University Düsseldorf
University of Florida
University of Bath
General Motors (United States)
University of Adelaide
University of Sydney
Rutgers, The State University of New Jersey
National Institutes of Health
Washington University in St. Louis
Stevens Institute of Technology
University of Sydney
Charles Sturt University
Brunel University London