World's Best Scientists 2026 revealed!

D-Index & Metrics

Computer Science

D-Index
45
Citations
11535
World Ranking
7063
National Ranking
62

Overview

Jung Ho Ahn is affiliated with Seoul National University in South Korea. Their research predominantly spans the field of Computer Science, with a strong focus on subfields such as Artificial Intelligence, Computer Networks and Communications, Electrical and Electronic Engineering, Hardware and Architecture, and Information Systems.

The scientist's work covers multiple main topics, including:

  • Parallel Computing and Optimization Techniques
  • Cryptography and Data Security
  • Advanced Data Storage Technologies
  • Ferroelectric and Negative Capacitance Devices
  • Cryptographic Implementations and Security
  • Advanced Neural Network Applications
  • Biodegradable Polymer Synthesis and Properties

Frequent publication venues for Jung Ho Ahn include:

  • IEEE Computer Architecture Letters
  • arXiv (Cornell University)
  • KIISE Transactions on Computing Practices
  • IEEE Access
  • Bioresource Technology

Some of the scientist's recent published papers are:

  • "Over 100x Faster Bootstrapping in Fully Homomorphic Encryption through Memory-centric Optimization with GPUs" (2021), published in IACR Transactions on Cryptographic Hardware and Embedded Systems
  • "Accelerating Fully Homomorphic Encryption Through Architecture-Centric Analysis and Optimization" (2021), published in IEEE Access
  • "CAT-TWO: Counter-Based Adaptive Tree, Time Window Optimized for DRAM Row-Hammer Prevention" (2020), published in IEEE Access
  • "MViD: Sparse Matrix-Vector Multiplication in Mobile DRAM for Accelerating Recurrent Neural Networks" (2020), published in IEEE Transactions on Computers
  • "BTS: An Accelerator for Bootstrappable Fully Homomorphic Encryption" (2021), published on arXiv (Cornell University)

The scientist collaborates regularly with:

  • Jaewan Choi
  • Eojin Lee
  • Jongmin Kim
  • Jaehyun Park
  • Wonkyung Jung

Best Publications

  • McPAT: an integrated power, area, and timing modeling framework for multicore and manycore architectures

    Sheng Li;Jung Ho Ahn;Richard D. Strong;Jay B. Brockman

  • Corona: System Implications of Emerging Nanophotonic Technology

    Dana Vantrease;Robert Schreiber;Matteo Monchiero;Moray McLaren

  • Merrimac: Supercomputing with Streams

    William J. Dally;Francois Labonte;Abhishek Das;Patrick Hanrahan

  • Programmable stream processors

    U.J. Kapasi;S. Rixner;W.J. Dally;B. Khailany

  • HyperX: topology, routing, and packaging of efficient large-scale networks

    Jung Ho Ahn;Nathan Binkert;Al Davis;Moray McLaren

  • NDA: Near-DRAM acceleration architecture leveraging commodity DRAM devices and standard memory modules

    Amin Farmahini-Farahani;Jung Ho Ahn;Katherine Morrow;Nam Sung Kim

  • A Comprehensive Memory Modeling Tool and Its Application to the Design and Analysis of Future Memory Hierarchies

    Shyamkumar Thoziyoor;Jung Ho Ahn;Matteo Monchiero;Jay B. Brockman

  • The McPAT Framework for Multicore and Manycore Architectures: Simultaneously Modeling Power, Area, and Timing

    Sheng Li;Jung Ho Ahn;Richard D. Strong;Jay B. Brockman

  • CACTI-P: architecture-level modeling for SRAM-based structures with advanced leakage reduction techniques

    Sheng Li;Ke Chen;Jung Ho Ahn;Jay B. Brockman

  • CACTI-3DD: architecture-level modeling for 3D die-stacked DRAM main memory

    Ke Chen;Sheng Li;Naveen Muralimanohar;Jung Ho Ahn

  • Devices and architectures for photonic chip-scale integration

    J. Ahn;M. Fiorentino;R. G. Beausoleil;N. Binkert

  • BTS: an accelerator for bootstrappable fully homomorphic encryption

    Unknown

  • Over 100x Faster Bootstrapping in Fully Homomorphic Encryption through Memory-centric Optimization with GPUs

    Unknown

  • Evaluating the Imagine Stream Architecture

    Jung Ho Ahn;William J. Dally;Brucek Khailany;Ujval J. Kapasi

  • McSimA+: A manycore simulator with application-level+ simulation and detailed microarchitecture modeling

    Jung Ho Ahn;Sheng Li;O. Seongil;Norman P. Jouppi

  • Memory-centric system interconnect design with hybrid memory cubes

    Gwangsun Kim;John Kim;Jung Ho Ahn;Jaeha Kim

  • Architecting to achieve a billion requests per second throughput on a single key-value store server platform

    Sheng Li;Hyeontaek Lim;Victor W. Lee;Jung Ho Ahn

  • ARK: Fully Homomorphic Encryption Accelerator with Runtime Data Generation and Inter-Operation Key Reuse

    Unknown

  • Future scaling of processor-memory interfaces

    Jung Ho Ahn;Norman P. Jouppi;Christos Kozyrakis;Jacob Leverich

  • Reducing memory access latency with asymmetric DRAM bank organizations

    Young Hoon Son;O. Seongil;Yuhwan Ro;Jae W. Lee

  • A Nanophotonic Interconnect for High-Performance Many-Core Computation

    R.G. Beausoleil;J. Ahn;N. Binkert;A. Davis

  • Chameleon: versatile and practical near-DRAM acceleration architecture for large memory systems

    Hadi Asghari-Moghaddam;Young Hoon Son;Jung Ho Ahn;Nam Sung Kim

  • Managing shared last-level cache in a heterogeneous multicore processor

    Gwangsun Kim;John Kim;Jung Ho Ahn;Jaeha Kim

Frequent Co-Authors

Norman P. Jouppi
Norman P. Jouppi Google (United States)
Robert Schreiber
Robert Schreiber Cerebras Systems
William J. Dally
William J. Dally Nvidia (United Kingdom)
Nam Sung Kim
Nam Sung Kim University of Illinois at Urbana-Champaign
John Kim
John Kim University of California, Los Angeles
Mattan Erez
Mattan Erez The University of Texas at Austin
Naveen Muralimanohar
Naveen Muralimanohar Google (United States)
Marco Fiorentino
Marco Fiorentino Hewlett Packard Enterprise (United States)
Raymond G. Beausoleil
Raymond G. Beausoleil Hewlett-Packard (United States)
Brucek Khailany
Brucek Khailany Nvidia (United States)

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