Donghyuk Lee focuses on Dram, Embedded system, CAS latency, Memory rank and Computer hardware. He combines subjects such as Latency, Memory bandwidth, Parallel computing, Bandwidth and Universal memory with his study of Dram. The concepts of his Universal memory study are interwoven with issues in Field-programmable gate array, Overhead and Data transmission.
His research integrates issues of Redundancy, Operating system and Error mitigation in his study of Embedded system. His research investigates the connection between CAS latency and topics such as Bottleneck that intersect with problems in Auxiliary memory. His Computer hardware study deals with Row intersecting with Memory controller and Multi-channel memory architecture.
Donghyuk Lee mostly deals with Dram, Artificial intelligence, Embedded system, Computer hardware and Computer vision. His Dram research includes elements of Latency, Efficient energy use, Memory rank, Universal memory and CAS latency. His Artificial intelligence research incorporates themes from Terminal, Natural language processing and Pattern recognition.
His Embedded system research incorporates elements of Exploit, Software, Memory controller and Double data rate. His Computer hardware research includes themes of Memory cell and Parallel computing. His research in the fields of Image, Object and Background image overlaps with other disciplines such as User input.
Donghyuk Lee mainly investigates Dram, Embedded system, Parallel computing, Latency and Memory controller. His Dram research is multidisciplinary, incorporating elements of Serialization, Energy consumption, Reliability engineering, Exploit and Efficient energy use. His research investigates the link between Efficient energy use and topics such as Cache that cross with problems in CAS latency and Sense amplifier.
His Parallel computing research is multidisciplinary, incorporating perspectives in Convolution, Deep learning and Convolutional neural network. His Latency study incorporates themes from Computer architecture, Row, Microarchitecture, Dram chip and Bottleneck. Donghyuk Lee studied Memory controller and Field-programmable gate array that intersect with Double data rate and Interface.
Dram, Parallel computing, Energy consumption, Reliability engineering and Latency are his primary areas of study. Donghyuk Lee combines topics linked to Microarchitecture with his work on Dram. The various areas that Donghyuk Lee examines in his Parallel computing study include Multiplication, Column and Convolutional neural network.
His Energy consumption research incorporates elements of CPU cache and Efficient energy use. His Reliability engineering research incorporates themes from Reliability, Bandwidth and Voltage. His Latency study combines topics in areas such as Multicore systems, Scheduling, Computer architecture and Serialization.
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Flipping bits in memory without accessing them: an experimental study of DRAM disturbance errors
Yoongu Kim;Ross Daly;Jeremie Kim;Chris Fallin.
international symposium on computer architecture (2014)
A case for exploiting subarray-level parallelism (SALP) in DRAM
Yoongu Kim;Vivek Seshadri;Donghyuk Lee;Jamie Liu.
international symposium on computer architecture (2012)
RowClone: fast and energy-efficient in-DRAM bulk data copy and initialization
Vivek Seshadri;Yoongu Kim;Chris Fallin;Donghyuk Lee.
international symposium on microarchitecture (2013)
Ambit: in-memory accelerator for bulk bitwise operations using commodity DRAM technology
Vivek Seshadri;Donghyuk Lee;Thomas Mullins;Hasan Hassan.
international symposium on microarchitecture (2017)
Tiered-latency DRAM: A low latency and low cost DRAM architecture
Donghyuk Lee;Yoongu Kim;V. Seshadri;Jamie Liu.
high-performance computer architecture (2013)
A 1.2 V 12.8 GB/s 2 Gb Mobile Wide-I/O DRAM With 4 $ imes$ 128 I/Os Using TSV Based Stacking
Jung-Sik Kim;Chi Sung Oh;Hocheol Lee;Donghyuk Lee.
international solid-state circuits conference (2011)
Improving DRAM performance by parallelizing refreshes with accesses
Kevin Kai-Wei Chang;Donghyuk Lee;Zeshan Chishti;Alaa R. Alameldeen.
high-performance computer architecture (2014)
Adaptive-latency DRAM: Optimizing DRAM timing for the common-case
Donghyuk Lee;Yoongu Kim;Gennady Pekhimenko;Samira Khan.
high-performance computer architecture (2015)
The efficacy of error mitigation techniques for DRAM retention failures: a comparative experimental study
Samira Khan;Donghyuk Lee;Yoongu Kim;Alaa R. Alameldeen.
measurement and modeling of computer systems (2014)
Fast Bulk Bitwise AND and OR in DRAM
Vivek Seshadri;Kevin Hsieh;Amirali Boroumand;Donghyuk Lee.
IEEE Computer Architecture Letters (2015)
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