Christopher B. Wilkerson mostly deals with Cache, Dram, Embedded system, CPU cache and Computer hardware. His is doing research in Cache pollution, Cache coloring and Cache algorithms, both of which are found in Cache. Parallel computing covers Christopher B. Wilkerson research in Cache pollution.
Christopher B. Wilkerson has researched Dram in several fields, including Memory rank, Data loss and Error mitigation. His work carried out in the field of CPU cache brings together such families of science as Low voltage, Random access memory, Energy per instruction and Locality of reference. His research investigates the connection with Field-programmable gate array and areas like Universal memory which intersect with concerns in CAS latency.
His primary scientific interests are in Cache, Parallel computing, Computer hardware, Embedded system and CPU cache. In general Parallel computing study, his work on Branch table often relates to the realm of Instruction window, thereby connecting several areas of interest. His Computer hardware research includes elements of Error detection and correction and Table.
His Embedded system study also includes
The scientist’s investigation covers issues in Cache, Computer hardware, CPU cache, Parallel computing and Embedded system. His Cache study is focused on Operating system in general. His biological study spans a wide range of topics, including Cache coloring and Voltage.
His work deals with themes such as State and Data transmission, which intersect with CPU cache. His work on Cache controller, Cache associativity and Write buffer as part of his general Parallel computing study is frequently connected to Block, thereby bridging the divide between different branches of science. His studies in Embedded system integrate themes in fields like Dram, Latency, Idle, Data loss and Efficient energy use.
His primary areas of investigation include Dram, Embedded system, Parallel computing, Cache and Operating system. The various areas that he examines in his Dram study include Random access memory, Memory rank, Physical address, Non-uniform memory access and Cache-only memory architecture. Memory rank is a subfield of Computer hardware that Christopher B. Wilkerson studies.
The Embedded system study combines topics in areas such as Universal memory, Latency, Error mitigation, Redundancy and Efficient energy use. He combines subjects such as Write combining and Aggregate with his study of Parallel computing. His research on Cache focuses in particular on Instruction prefetch.
This overview was generated by a machine learning system which analysed the scientist’s body of work. If you have any feedback, you can contact us here.
Flipping bits in memory without accessing them: an experimental study of DRAM disturbance errors
Yoongu Kim;Ross Daly;Jeremie Kim;Chris Fallin.
international symposium on computer architecture (2014)
Value locality and load value prediction
Mikko H. Lipasti;Christopher B. Wilkerson;John Paul Shen.
architectural support for programming languages and operating systems (1996)
Runahead execution: an alternative to very large instruction windows for out-of-order processors
O. Mutlu;J. Stark;C. Wilkerson;Y.N. Patt.
high-performance computer architecture (2003)
Energy-Efficient and Metastability-Immune Resilient Circuits for Dynamic Variation Tolerance
Keith A. Bowman;James W. Tschanz;Nam Sung Kim;Janice C. Lee.
international solid-state circuits conference (2009)
Trading off Cache Capacity for Reliability to Enable Low Voltage Operation
Chris Wilkerson;Hongliang Gao;Alaa R. Alameldeen;Zeshan Chishti.
international symposium on computer architecture (2008)
An experimental study of data retention behavior in modern DRAM devices: implications for retention time profiling mechanisms
Jamie Liu;Ben Jaiyen;Yoongu Kim;Chris Wilkerson.
international symposium on computer architecture (2013)
A 45 nm Resilient Microprocessor Core for Dynamic Variation Tolerance
K A Bowman;J W Tschanz;S L Lu;P A Aseron.
IEEE Journal of Solid-state Circuits (2011)
Reducing cache power with low-cost, multi-bit error-correcting codes
Chris Wilkerson;Alaa R. Alameldeen;Zeshan Chishti;Wei Wu.
international symposium on computer architecture (2010)
Scheduling threads for constructive cache sharing on CMPs
Shimin Chen;Phillip B. Gibbons;Michael Kozuch;Vasileios Liaskovitis.
acm symposium on parallel algorithms and architectures (2007)
Improving DRAM performance by parallelizing refreshes with accesses
Kevin Kai-Wei Chang;Donghyuk Lee;Zeshan Chishti;Alaa R. Alameldeen.
high-performance computer architecture (2014)
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