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Computer Science

D-Index
43
Citations
9306
World Ranking
7886
National Ranking
472

Overview

Chris Wilkerson is affiliated with Nvidia in the United States and focuses on research within the field of Computer Science. The scientist's work spans several subfields including Artificial Intelligence, Computer Networks and Communications, and Information Systems.

Their main research topics address areas such as Cryptography and Data Security, Advanced Data Storage Technologies, Cloud Data Security Solutions, and Cryptographic Implementations and Security. These topics reflect involvement in both theoretical and applied aspects of secure computing and data protection.

Chris Wilkerson has published multiple papers in notable venues. Recent publications include:

  • FHEmem: A Processing In-Memory Accelerator for Fully Homomorphic Encryption, 2025, IEEE Transactions on Emerging Topics in Computing
  • FHEmem: A Processing In-Memory Accelerator for Fully Homomorphic Encryption, 2023, arXiv (Cornell University)
  • Special Issue on Contemporary Industry Products 2025, 2025, IEEE Micro

Their research collaboration network features frequent coauthors such as Minxuan Zhou, Pranav Gangwar, Weihong Xu, Arpan Dutta, and Saransh Gupta. These colleagues have jointly contributed to several projects and publications, indicating a collaborative approach to research in the domain.

Chris Wilkerson's work has appeared primarily in these publication venues:

  • IEEE Transactions on Emerging Topics in Computing
  • arXiv (Cornell University)
  • IEEE Micro

Best Publications

  • Flipping bits in memory without accessing them: an experimental study of DRAM disturbance errors

    Yoongu Kim;Ross Daly;Jeremie Kim;Chris Fallin

  • Value locality and load value prediction

    Mikko H. Lipasti;Christopher B. Wilkerson;John Paul Shen

  • Runahead execution: an alternative to very large instruction windows for out-of-order processors

    O. Mutlu;J. Stark;C. Wilkerson;Y.N. Patt

  • Energy-Efficient and Metastability-Immune Resilient Circuits for Dynamic Variation Tolerance

    Keith A. Bowman;James W. Tschanz;Nam Sung Kim;Janice C. Lee

  • An experimental study of data retention behavior in modern DRAM devices: implications for retention time profiling mechanisms

    Jamie Liu;Ben Jaiyen;Yoongu Kim;Chris Wilkerson

  • Trading off Cache Capacity for Reliability to Enable Low Voltage Operation

    Chris Wilkerson;Hongliang Gao;Alaa R. Alameldeen;Zeshan Chishti

  • A 45 nm Resilient Microprocessor Core for Dynamic Variation Tolerance

    K A Bowman;J W Tschanz;S L Lu;P A Aseron

  • Reducing cache power with low-cost, multi-bit error-correcting codes

    Chris Wilkerson;Alaa R. Alameldeen;Zeshan Chishti;Wei Wu

  • Improving DRAM performance by parallelizing refreshes with accesses

    Kevin Kai-Wei Chang;Donghyuk Lee;Zeshan Chishti;Alaa R. Alameldeen

  • Scheduling threads for constructive cache sharing on CMPs

    Shimin Chen;Phillip B. Gibbons;Michael Kozuch;Vasileios Liaskovitis

  • Improving cache lifetime reliability at ultra-low voltages

    Zeshan Chishti;Alaa R. Alameldeen;Chris Wilkerson;Wei Wu

  • Energy-efficient cache design using variable-strength error-correcting codes

    Alaa R. Alameldeen;Ilya Wagner;Zeshan Chishti;Wei Wu

  • Exploiting spatial locality in data caches using spatial footprints

    Sanjeev Kumar;Christopher Wilkerson

  • The efficacy of error mitigation techniques for DRAM retention failures: a comparative experimental study

    Samira Khan;Donghyuk Lee;Yoongu Kim;Alaa R. Alameldeen

  • Efficiently prefetching complex address patterns

    Manjunath Shevgoor;Sahil Koladiya;Rajeev Balasubramonian;Chris Wilkerson

  • Circuit techniques for dynamic variation tolerance

    Keith Bowman;James Tschanz;Chris Wilkerson;Shih-Lien Lu

  • Transparent Hardware Management of Stacked DRAM as Part of Memory

    Jaewoong Sim;Alaa R. Alameldeen;Zeshan Chishti;Chris Wilkerson

  • Sandbox Prefetching: Safe run-time evaluation of aggressive prefetchers

    Seth H Pugsley;Zeshan Chishti;Chris Wilkerson;Peng-fei Chuang

  • MorphCore: An Energy-Efficient Microarchitecture for High Performance ILP and High Throughput TLP

    Khubaib;M. Aater Suleman;Milad Hashemi;Chris Wilkerson

  • Runahead execution: An effective alternative to large instruction windows

    O. Mutlu;J. Stark;C. Wilkerson;Y.N. Patt

  • Path confidence based lookahead prefetching

    Jinchun Kim;Seth H. Pugsley;Paul V. Gratz;A. L. Narasimha Reddy

Frequent Co-Authors

Alaa R. Alameldeen
Alaa R. Alameldeen Intel (United States)
Shih-Lien Lu
Shih-Lien Lu Washington State University
Keith Bowman
Keith Bowman Qualcomm (United States)
James W. Tschanz
James W. Tschanz Intel (United States)
Tanay Karnik
Tanay Karnik Intel (United States)
Onur Mutlu
Onur Mutlu ETH Zurich
Vivek De
Vivek De Intel (United States)
Muhammad M. Khellah
Muhammad M. Khellah Intel (United States)
Donghyuk Lee
Donghyuk Lee Nvidia (United States)
Dinesh Somasekhar
Dinesh Somasekhar Intel (United States)

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